EUV resists, while improving steadily, generate a number of nanobridge or break defects that increases quickly as the pitch approaches 30 nm. Inline inspection methods are therefore needed to reliably detect patterning defects smaller than 20 nm. Massive e-beam metrology provides the high resolution needed to measure these defects, while remaining compatible with HVM throughput requirements. In this work, we used a direct metal (Ru) etch process, to fabricate EUV-patterned electrical structures in the 32 nm-36 nm pitch range. We demonstrate an almost one-to-one correspondence between the e-beam metrology yield of the structures, and their electrical yield. The e-beam inspection is realized with a large-field-of-view HMI eP5 e-beam system. The match between e-beam and electrical yield shows that our e-beam inspection is able to catch all electrically relevant line breaks, while excluding false flags. These results demonstrate the capability of massive e-beam inspection in predicting electrical yield.
In this work we show measurement results on EUV vias through full process integration; after litho (ADI), after etch (AEI) and after CMP polish (API) for a wide range of designs (regular arrays, logic, SRAM, and alignment and overlay mark designs) on a single damascene via scheme.
Physical inspection (top view) and voltage contrast (VC) measurements are used to determine number of via failures at different stages of the process flow. While the physical inspection reveals vias missing and merging on top layer (at resist level ADI or hard mask AEI) the VC also can show failing vias AEI at the bottom of the via or in general failing vias API due to failing via fill during metallization and etch.
Different metallization schemes including TaN vs TaNRu liners and Co vs Cu plating and CMP were compared using VC. Quantification of VC anomalies in the inspection images allows judgement of the metal fill on the single damascene via patterning across the different structures. The number of missing and merging vias AEI and API is used as a proxy for yield and this metric was used to drive process optimization.
Given the large FoV of images collected on eP5 tool with a field of view 8µm x 8µm - 12µm x 12µm with 1nm or 2nm pixel size it is possible to determine both CD and defects in the same inspection for a substantial number of vias in a relatively short inspection time. Furthermore the VC inspection method is applied to an imec vehicle consisting of via chains at 32nm pitch to determine and localize failures along the via chain.
With the adoption of extreme ultraviolet (EUV) lithography in high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, defect characterization brings new challenges and learnings. Traditional approaches to process window discovery (PWD) methodology developed2,3,4 using broadband plasma optical inspection also hold in the realm of EUV lithography. Although there is substantial depth of focus for regular patterns, focus continues to be an important modulation parameter for logic patterns. Dose is an important modulation parameter especially due to stochastic defects.1 Further, overlay is another important parameter when it comes to hybrid integration schemes such as self-aligned quadruple patterning (SAQP) and EUV block patterning, for example, in BEOL layers. In this paper, we will discuss PWD results on a foundry N5 equivalent M2 layer, studying both SAQP and block integration with direct EUV patterning. We also demonstrate the impact of EUV stochastics to the overall process window and develop useful analysis methodologies.
This paper uses Virtual Fabrication to assess the imec 7 nm node (iN7) Self-Aligned Quadruple Patterning (SAQP) integration scheme for the 16 nm half-pitch Metal 2 line formation. We present first the technical challenge of obtaining defect-free M2 lines with SAQP, and then provide a solution to achieve a <1% failure rate using a combination of Advanced Process Control and Virtual Fabrication.
The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations.
Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers.
In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.
imec’s investigation on EUV single patterning insertion into industry 5nm-relevant logic metal layer is discussed. Achievement and challenge across imaging, OPC, mask data preparation and resulting wafer pattern fidelity are reported with a broad scope.
Best focus shift by mask 3D of isolated feature gets worse by the insertion of SRAF, which puts a negative impact on obtaining large overlap process window across features. imec’s effort across OPC including SMO and mask sizing is discussed with mask rule that affects mask writing. Resist stochastic induced defect is identified as a biggest challenge during the overall optimization, and options to overcome the challenge is investigated. For mask data preparation, dramatic increase in the data volume in EUV mask manufacturing is observed from iArF multiple patterning to EUV single patterning conversion, particularly by the insertion of SRAF. In addition, logic design consideration to make EUV single patterning more affordable compared to alternative patterning option is be discussed.
imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node
equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both
iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of
42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling
boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it
makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask
sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated
for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell
design, integration and patterning specification are discussed.
Proc. SPIE. 10143, Extreme Ultraviolet (EUV) Lithography VIII
KEYWORDS: Lithography, Logic, Optical lithography, Etching, Metals, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Double patterning technology, Critical dimension metrology, Semiconducting wafers, Stochastic processes, System on a chip, Back end of line
The imec N7 (iN7) platform has been developed to evaluate EUV patterning of advanced logic BEOL layers. Its design is based on a 42 nm first-level metal (M1) pitch, and a 32 nm pitch for the subsequent M2 layer. With these pitches, the iN7 node is an ‘aggressive’ full-scaled N7, corresponding to IDM N7, or foundry N5.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
This paper summarizes findings on the iN7 platform (foundry N5 equivalent) for single exposure EUV (SE EUV) of M1 and M2 BEOL layers. Logic structures within these layers have been measured after litho and after etch, and variability was characterized both with conventional CD-SEM measurements as well as Hitachi contouring method. After analyzing the patterning of these layers, the impact of variability on potential interconnect reliability was studied by using MonteCarlo and process emulation simulations to determine if current litho/etch performance would meet success criteria for the given platform design rules.
Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.
To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.
Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.