With the integration of high energy ion implant processes into volume CMOS manufacturing, the need for thick resist stabilization to achieve a stable ion implant process is critical. With new photoresist characteristics, new implant end station characteristics arise. The resist outgassing needs to be addressed as well as the implant profile to ensure that the dosage is correct and the implant angle does not interfere with other underlying features. This study compares conventional deep-UV/thermal with electron beam stabilization. The electron beam system used in this study utilizes a flood electron source and is a non-thermal process. These stabilization techniques are applied to a MeV ion implant process in a CMOS production process flow.
Patterning photoresists on reflective topography such as aluminum is one of the more difficult problems in device manufacturing. Interference effects caused by reflected light from the substrate/photoresist interface and surface topography result in coupling of additional energy into the film. This leads to linewidth variation known as reflective notching which severely impacts process latitude and increases critical dimension variation. For many years, suppliers approached the problem by adding dyes that absorb in the actinic region to create a larger non-bleachable absorption. In recent years, strongly absorbing intermediate layers or ARC's, both organic and inorganic, have seen widespread implementation to control reflective notching. However, if a fab is not equipped to accommodate the required ARC process, the processing can be very time consuming, cumbersome and costly. This study was undertaken to determine if a non-ARC, i-line photoresist process could be developed to reduce or eliminate aluminum reflective notching and accompanying critical dimension variation. This study was designed to screen, identify, and characterize various resist chemistries. Based on the screening characterization, a final, cost effective resist chemistry without ARC was selected, fully characterized and transferred into production. The selected material is currently being used in a high volume 0.60 micrometers CMOS, 200 mm wafer manufacturing process.
Conference Committee Involvement (1)
Data Analysis and Modeling for Patterning Control III
23 February 2006 | San Jose, California, United States