Data volume and average data preparation time continue to trend upward with newer technology nodes. In the past decade, with file sizes measured in terabytes and network bandwidth requirements exceeding 40GB/s, mask synthesis operations have expanded their cluster capacity to thousands and even 10s of thousands of CPU cores. Efficient, scalable and flexible management of this expensive, high performance, distributed computing system is required in every stage of geometry processing - from layout polishing through Optical Proximity Correction (OPC), Mask Process Correction (MPC) and Mask Data Preparation (MDP) - to consistently meet tape out cycle time goals. The MDP step, being the final stage in the entire flow, has to write all of the pattern data into one or more disk files. This extremely I/O intensive section remains a significant portion of the processing time and creates a major challenge for the software from a scalability perspective. It is important to have a comprehensive solution that displays high scalability for large jobs and low overhead for small jobs, which is the ideal behavior in a typical production environment. In this paper we will discuss methods to address the former requirement, emphasizing the efficient use of high performance distributed file systems while minimizing the less scalable disk I/O operations. We will also discuss dynamic resource management and efficient job scheduling to address the latter requirement. Finally, we will demonstrate the use of a cluster management system to create a comprehensive data processing environment suitable to support large scale data processing requirements.
With CMOS technology nodes going further into the realm of sub-wavelength lithography, the need for compute power also increases to meet runtime requirements for reticle enhancement techniques and results validation. Expanding the mask data preparation (MDP) cluster size is an obvious solution to increase compute power, but this can lead to unforeseen events such as network bottlenecks, which must be taken into account. Advanced scalable solutions provided by optical proximity correction (OPC)/mask process correction (MPC) software are obviously critical, but other optimizations such as dynamic CPU allocations (DCA) based on real CPU needs, high-level jobs management, real-time resource monitoring, and bottleneck detection are also important factors for improving cluster utilization in order to meet runtime requirements and handle post-tapeout (PTO) workloads efficiently. In this paper, we will discuss tackling such efforts through various levels of the “cluster utilization stack” from low CPU levels to business levels to head towards maximizing cluster utilization and maintaining lean computing.
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Semiconductors, Visualization, Manufacturing, Data processing, Photomasks, Integrated circuits, Optical proximity correction, Back end of line, Front end of line, Design for manufacturability
Delivering mask ready OPC corrected data to the mask shop on-time is critical for a foundry to meet the cycle time commitment for a new product. With current OPC compute resource sharing technology, different job scheduling algorithms are possible, such as, priority based resource allocation and fair share resource allocation. In order to maximize computer cluster efficiency, minimize the cost of the data processing and deliver data on schedule, the trade-offs of each scheduling algorithm need to be understood. Using actual production jobs, each of the scheduling algorithms will be tested in a production tape-out environment. Each scheduling algorithm will be judged on its ability to deliver data on schedule and the trade-offs associated with each method will be analyzed. It is now possible to introduce advance scheduling algorithms to the OPC data processing environment to meet the goals of on-time delivery of mask ready OPC data while maximizing efficiency and reducing cost.
Mask manufacturers are continuously challenged as a result of the explosive growth in mask pattern data volume.
This paper presents a new pipelined approach to mask data preparation for inspection that significantly reduces the
data preparation times compared to the conventional flows used today. The focus of this approach minimizes I/O
bottlenecks and allows for higher throughput on computer clusters. This solution is optimized for the industry
standard OASIS.MASK format.
These enhancements in the data processing flow, along with optimizations in the data preparation system
architecture, offer a more efficient and highly scalable solution for mask inspection data preparation.
The increasing demands for registration metrology for repeatability, accuracy, and resolution in order to be able to
perform measurements in the active area on production features have prompted the development of PROVE<sup>TM</sup>, the nextgeneration
registration metrology tool that utilizes 193nm illumination and a metrology stage that is actively controlled
in all six degrees of freedom. PROVE<sup>TM</sup> addresses full in-die capability for double patterning lithography and
sophisticated inverse-lithography schemes. Innovative approaches for image analysis, such as 2D correlation, have
been developed to achieve this demanding goal.
In order to take full advantage of the PROVE<sup>TM</sup> resolution and measurement capabilities, a direct link to the mask data
preparation for job automation and marker identification is inevitable. This paper describes an integrated solution using
Synopsys' CATS<sup>R</sup> for extracting and preparing tool-specific job input data for PROVE. In addition to the standard
marking functionalities, CATS<sup>R</sup> supports the 2D correlation method by providing reference clips in OASIS.MASK
Double Patterning Lithography (DPL) for next generation wafer exposure is placing greater demands on the
requirements for pattern placement accuracy on photomasks. Recent studies have shown that pattern placement accuracy
can be one of the largest components of systematic wafer overlay error. Since LELE or LFLE DPL technologies tighten
intra-field-wafer overlay requirements by as much as a factor of 2 (to 2 - 3nm for critical layers), minimizing all sources
of systematic overlay error has become critical. In addition to its impact on overlay performance, any significant pattern
displacement between the two exposures in a double patterning scheme will have a significant impact on CD uniformity,
another major area of concern for next-generation devices.
In the past, mask registration has been referenced to design data using relatively large, specially designed targets.
However, as shown in many previous papers , the true registration error of a next-generation reticle cannot be
sufficiently described by using today's sampling plans. In order to address this issue, it is mandatory to have In-Die
registration capability for next generation reticle registration. On this path to In-Die pattern placement metrology many
challenges have to be solved. One is the data preparation necessary to get the targets placed and marked within the
design, preparing for the later metrology step.
This paper demonstrates an automated way of performing In-Die registration metrology. This new approach allows more
flexible and higher density metrology so that pattern placement error is sufficiently well characterized.
As technology nodes go down to 45nm and below, mask metrology becomes more important as the critical features
decrease in size, while, at the same time, the number of measurements that need to be performed increases. OPC and
RET put further burden on metrology as it is typical to measure more than one dimension on a single feature. In order to
maximize the throughput of metrology tools and to keep up with the demand for more measurements, we have
implemented the ability to measure multiple CD sites within a field of view without any stage movement in fully
automated ways in a production environment. This in turn reduces total mask measurement time and helps to increase