This paper presents adder circuits of various architectures aimed at reducing static power dissipation. Circuit
topologies for basic building blocks were evaluated for fabrication technologies of 65nm down to 32nm, and
simulation results are presented. This work has lead to the development of various low power adder circuits and
provides comparative analysis leading to the recommendation that a variable size block carry select adder is the
best performer, taking into consideration both static and dynamic power dissipation.