This past year has witnessed a sharp increase in EUV lithography progress spanning production tools, source and infrastructure to better position the technology for HVM readiness. While the exposure source remains the largest contributor to downtime and availability, significant strides in demonstrated source power have bolstered confidence in the viability of EUVL for insertion into HVM production. The ongoing development of an EUV pellicle solution alleviates industry concern about one significant source of line-yield risk. In addition to continued expected improvements in EUV source power and availability, the ability to deliver predictable yield remains an ultimate gate to HVM insertion. Ensuring predictable yield requires significant emphasis on reticles. This includes continued pellicle development to enable the readiness and supply of a robust pellicle solution in advance of 250W source power, as well as improvements in mask blank defectivity and techniques to detect and mitigate reticle blank and pattern defects.
When compared to a thick absorber mask, a thin absorber EUV mask is expected to have a comparable process
window, a reduced shadowing effect, and lower MEEF. However, regardless of the mask absorber thickness, the
dark-field in EUV lithography is never 100% dark. Using the same absorber stack composition, EUV masks with
thinner absorbers have inherently higher leakage due to the background transmission propagating through the absorber
stack. While this does act to improve resist sensitivity or throughput, the leakage reduces the image contrast and can
cause CD degradation in "double" exposed regions at the edge of adjacent fields. In this study, EUVL lithographic
benchmarking of both thin and thick absorber masks on the ASML Alpha Demo Tool (ADT) at IMEC is presented.
Herein, we experimentally quantify the process window, EL, LWR, MEEF, E<sub>size</sub>, ultimate resolution, and impact of
dark-field background exposures on CDs for both thin and thick absorber masks. There are additional issues when
field edges overlap with adjacent fields, and mitigation strategies for EUV leakage emanating from dark-field regions
EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices
. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule
restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and
lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to
demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper
yield. A patterning demonstration of Intel's 32 nm test chips using the ADT at IMEC  is presented, This test chip
was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intel's mask
shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT
which resulted in a large k<sub>1</sub> factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It
was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these
originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist,
overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.
EUV blank non-flatness results in both out of plane distortion (OPD) and in-plane distortion (IPD) [3-5]. Even for extremely flat masks (~50 nm peak to valley (PV)), the overlay error is estimated to be greater than the allocation in the overlay budget. In addition, due to multilayer and other thin film induced stresses, EUV masks have severe bow (~1 um PV). Since there is no electrostatic chuck to flatten the mask during the e-beam write step, EUV masks are written in a bent state that can result in ~15 nm of overlay error. In this article we present the use of physically-based models of mask bending and non-flatness induced overlay errors, to compensate for pattern placement of EUV masks during the e-beam write step in a process we refer to as E-beam Writer based Overlay error Correction (EWOC). This work could result in less restrictive tolerances for the mask blank non-flatness specs which in turn would result in less blank defects.
Control of registration (overlay error between printed layers) is a key aspect of successfully manufacturing semiconductors. At Intel, registration control was formerly achieved through manual adjustments of the tool to account for the known effects of non-stationary drift. The objective of the stepper registration control (SRC) project was to create a robust algorithm and automated implementation to replace the manual adjustment process. This goal was accomplished at Intel by developing an automated product called SRC. At the heart of the SRC application is the SRC feedback algorithm. At the stepper, alignment settings are adjusted to correct for non-stationary drift. The SRC algorithm uses a weighted average of registration data from previous lots to determine the recommended alignment settings. The novel scheme weights prior lots using a combination of traditional EWMA based weighting and variance based weighting. After piloting and comparing the results against the manual algorithm, the SRC application has been shown to be at least as good as the manual algorithm. Thus the SRC application is being used by all 300mm Intel factories. Since HVM factories cannot resource the same level of frequent manual adjustments, the benefits of reduced rework rate and increased process capability is more pronounced in HVM.
Proc. SPIE. 5044, Advanced Process Control and Automation
KEYWORDS: Detection and tracking algorithms, Data modeling, Manufacturing, Control systems, Process control, Semiconductor manufacturing, Algorithm development, Feedback control, Process modeling, Correlation function
Control of DCCDs (Develop Check Critical Dimension) is a key aspect of successfully manufacturing semiconductors at Intel. DCCD control was formerly achieved through manual adjustments of the exposure dose on the tool to account for the known effects of non-stationary tool/process drift. An automated application EFCC (Exposure-Focus CD Control) was developed at Intel, to create a robust algorithm and automated implementation, replacing the manual adjustment process.
The EFCC algorithm uses DCCD summary measurements as the feedback to the stepper. At the stepper, the exposure setting is adjusted to correct for non-stationary tool/process drift. A weighted average of data from previous lots is used to determine the recommended exposure dose settings. The feedback scheme weights prior lots using a combination of traditional EWMA based weighting and within lot (across sites on wafer) variance based weighting.
The EFCC implementation has benefits in increased Cpk, reduced rework, continuous adjustment. Futhermore, as this is an automated control solution, it can easily be extended to support more sophisticated adjustment algorithms.