Large-area microelectronic applications require high-performance thin-film transistors for driver circuits. This is especially true in the case of "system-on-panel" applications where high levels of circuit integration are required to drive displays and sensors that are built onto the panel. While there are many methods that might be employed to crystallize Si films on lost-cost, high-temperature-intolerant substrates, very few offer the high performance characteristics that the applications demand. In this paper, we show that directionally solidified Si films can be readily used to fabricate high performance electronic devices for circuit applications. By only crystallizing those regions of the Si films that are used in the actual fabrication of TFTs, we show that many of the issues concerning low throughput rates can be avoided. Results from a CMOS ring oscillator showcasing the speed capability of such active layers are also presented.
For laser crystallization of amorphous silicon, plasma enhanced chemical vapor deposition (PECVD) is the method of choice for a-Si precursor deposition. This situation is likely to change, however, with the transition to higher performance polysilicon material produced via advanced laser annealing techniques. Two factors make the use of sputtered a-Si precursors particularly attractive for laser annealing technologies. First, owing to their low hydrogen content, sputtered a-Si films are uniquely suited as precursors for laser crystallization techniques. Second, the ability to dope the target material (and thus produce doped silicon films) allows for control of the threshold voltage of the resulting TFTs. To that end we evaluated sputter deposited doped silicon as an a-Si precursor for excimer laser annealing. We established process conditions necessary to shift the Vth of both N and P transistors such that they were centered near zero. In addition we determined levels of target doping, DC power, and chamber pressure that produced TFT's with balanced N and P Vth values and satisfactory mobility. We also found that the off-state leakage and subthreshold slope of the PVD films were better than PECVD deposited films.
We report on the fabrication and characterization of SiO2 thin films by high-density plasma enhanced chemical vapor deposition (HD-PECVD) technique at a processing temperature lower than 400°C for gate dielectric applications in thin film transistor (TFT) devices. An inductively coupled plasma source was used to couple the rf power to the top electrode. The SiO2 thin films were fabricated on p-Si wafers using nitrogen, nitrous oxide, and silane precursors. The deposition process was optimized in terms of the effects of rf power, gas flow rates, and system pressure on deposition rate, chemical etch rate, optical properties, and electrical characteristics. The effects of the processing variables on the refractive index, Si-O bond formation, and impurity related bonds were analyzed. The electrical properties of the films were evaluated from the I-V and C-V characteristics of the MOS capacitors. The effects of the SiO2 film thickness on the electrical characteristics of MOS capacitors were also investigated in the range of 30-100 nm. The influence of the low temperature processed gate dielectric on the performance of 500 Å poly-Si TFTs was evaluated in terms of the transfer and gate leakage characteristics. The microstructural and electrical characteristics of the HD-PECVD deposited SiO2 thin films suggest their suitability for the low temperature integration of TFTs on glass or other low temperature substrates.