We have previously discussed the potential of using a Hg<sub>1-x</sub>Cd<sub>x</sub>Te source as a reference plane for the non-uniformity
correction of thermal imagers and which is being developed as an option for the UK 3rd generation, high performance
thermal imaging program (Albion). In this paper we will present our first results on a large area (1.5 cm x 1.5 cm) source
which was grown on a silicon substrate and can simulate a range of temperatures from -10 °C to +30 °C. Due to the fast
switching speed, the apparent temperature can be changed on a frame by frame basis. Also, the operation of the device
can be synchronized to the integration time of the camera to reduce the mean power requirements by a factor of 10 and
reduce thermal heating effects. The main applications for Hg<sub>1-x</sub>Cd<sub>x</sub>Te devices as high-performance, cryogenically-cooled
detectors typically require very low drive currents. The use of this material for large-area LEDs has generated new
challenges to deal with the high peak currents. These are typically in the range 1-2 A/cm<sup>2</sup> for a MWIR waveband source
and have led to a need to reduce the common impedance, reduce the contact resistances and consider the effects of
Negative luminescent (NL) devices, which to an IR observer can appear colder than they actually are, have a wide range of possible applications, including use as modulated IR sources in gas sensing systems and as thermal radiation shields in IR cameras. A further important use would be a calibration source for IR focal plane arrays where there are many potential advantages over conventional sources, including high speed operation (for multi-point correction) and lower power consumption. Such applications present considerable technological challenges as they require large area uniform devices (>1cm<sup>2</sup>) with a large apparent temperature range.
In this paper we report on recent progress in fabricating large area (1.5cm × 1.5cm) negative luminescence devices from Hg<sub>1-x</sub>Cd<sub>x</sub>Te grown on silicon substrates using a segmented device architecture.