Die-to-Model (D2M) inspection is an innovative approach to running inspection based on a mask design layout data. The
D2M concept takes inspection from the traditional domain of mask pattern to the preferred domain of the wafer aerial
image. To achieve this, D2M transforms the mask layout database into a resist plane aerial image, which in turn is
compared to the aerial image of the mask, captured by the inspection optics.
D2M detection algorithms work similarly to an Aerial D2D (die-to-die) inspection, but instead of comparing a die to
another die it is compared to the aerial image model. D2M is used whenever D2D inspection is not practical (e.g., single
die) or when a validation of mask conformity to design is needed, i.e., for printed pattern fidelity. D2M is of particular
importance for inspection of logic single die masks, where no simplifying assumption of pattern periodicity may be
done. The application can tailor the sensitivity to meet the needs at different locations, such as device area, scribe lines
In this paper we present first test results of the D2M mask inspection application at a mask shop. We describe the
methodology of using D2M, and review the practical aspects of the D2M mask inspection.
With each new process technology node, chip designs increase in complexity and size, leading to a steady
increase in data volumes. As a result, mask data prep flows require more computing resources to maintain
the desired turn-around time (TAT) at a low cost. The effect is aggravated by the fact that a mask house
operates a variety of equipment for mask writing, inspection and metrology - all of which, until now,
require specific data formatting. An industry initiative sponsored by SEMI® has established new public
formats - OASIS® (P39) for general layouts and OASIS.MASK (P44) for mask manufacturing equipment -
that allow for the smallest possible representation of data for various applications. This paper will review a
mask data preparation process for mask inspection based on the OASIS formats that also reads
OASIS.MASK files directly in real time into the inspection tool. An implementation based on standard
parallelized computer hardware will be described and characterized as demonstrating throughputs required
for the 45nm and 32nm technology nodes. An inspection test case will also be reviewed.