Although technical issues remain to be resolved, EUV lithography is now a serious contender for critical
layer patterning of upcoming 2X node memory and 14nm Logic technologies in manufacturing. If
improvements continue in defectivity, throughput and resolution, then EUV lithography appears that it will
be the most extendable and the cost-effective manufacturing lithography solution for sub-78nm pitch
complex patterns. EUV lithography will be able to provide a significant relaxation in lithographic K1
factor (and a corresponding simplification of process complexity) vs. existing 193nm lithography. The
increased K1 factor will result in some complexity reduction for mask synthesis flow elements (including
illumination source shape optimization, design pre-processing, RET, OPC and OPC verification).
However, EUV does add well known additional complexities and issues to mask synthesis flows such as
across-lens shadowing variation, across reticle flare variation, new proximity effects to be modeled,
significant increase in pre-OPC and fracture file size, etc.
In this paper, we investigate the expected EUV-specific issues and new requirements for a production
tapeout mask synthesis flow. The production EUV issues and new requirements are in the categories of
additional physical effects to be corrected for; additional automation or flow steps needed; and increase in
file size at different parts in the flow. For example, OASIS file sizes after OPC of 250GigaBytes (GB) and
files sizes after mask data prep of greater than three TeraBytes (TB) are expected to be common. These
huge file sizes will place significant stress on post-processing methods, OPC verification, mask data
fracture, file read-in/read-out, data transfer between sites (e.g., to the maskshop), etc. With current methods
and procedures, it is clear that the hours/days needed to complete EUV mask synthesis mask data flows
would significantly increase if steps are not taken to make efficiency improvements. Therefore, we also
analyze different options for reducing or alleviating the EUV specific issues mentioned above and the
expected cost/benefit tradeoffs associated with these options. The options include understanding the
accuracy vs. run-time benefit of different rule-based and model-based approaches for several correction
issues; predicting the implications and improvements expected with different flow automation options; and
estimating possible productivity improvements with different flow parallelization choices and upcoming
multi-core processors. Optimal combinations of options and accuracy/effort/runtime results can be seen to
enable EUV lithography tapeout flows to achieve equal or better total time when compared to current
193nm optical lithography tapeout flow times.
Generally speaking, the models used in the optical proximity effect correction (OPC) can be divided into three parts,
mask part, optic part, and resist part. For the excellent quality of the OPC model, each part has to be described by the
first principles. However, OPC model can't take the all of the principles since it should cover the full chip level
calculation during the correction. Moreover, the calculation has to be done iteratively during the correction until the cost
function we want to minimize converges. Normally the optic part in OPC model is described with the sum of coherent
system (SOCS) method. Thanks to this method we can calculate the aerial image so fast without the significant loss of
accuracy. As for the resist part, the first principle is too complex to implement in detail, so it is normally expressed in a
simple way, such as the approximation of the first principles, and the linear combinations of factors which is highly
correlated with the chemistries in the resist. The quality of this kind of the resist model depends on how well we train the
model through fitting to the empirical data. The most popular way of making the mask function is based on the
Kirchhoff's thin mask approximation. This method works well when the feature size on the mask is sufficiently large,
but as the line width of the semiconductor circuit becomes smaller, this method causes significant error due to the mask
topography effect. To consider the mask topography effect accurately, we have to use rigorous methods of calculating
the mask function, such as finite difference time domain (FDTD) and rigorous coupled-wave analysis (RCWA). But
these methods are too time-consuming to be used as a part of the OPC model. Until now many alternatives have been
suggested as the efficient way of considering the mask topography effect. Among them we focused on the boundary
layer model (BLM) in this paper. We mainly investigated the way of optimization of the parameters for the BLM since
the feasibility of the BLM has been investigated in many papers. Instead of fitting the parameters to the wafer
critical dimensions (CD) directly, we tried to use the aerial image (AI) from the rigorous simulator with the
electromagnetic field (EMF) solver. Usually that kind of method is known as the staged modeling method. To see the
advantages of this method we conducted several experiments and observed the results comparing the method of fitting to
the wafer CD directly. Through the tests we could observe some remarkable results and confirmed that the staged
modeling had better performance in many ways.
GDSII is a data format of the circuit design file for producing semiconductor. GDSII is also used as a transfer format for
fabricating photo mask as well. As design rules are getting smaller and RET (Resolution Enhancement Technology) is
getting more complicated, the time of converting GDSII to a mask data format has been increased, which influences the
period of mask production. Photo mask shops all over the world are widely using computer clusters which are connected
through a network, that is, called distributed computing method, to reduce the converting time. Commonly computing
resource for conversion is assigned based on the input file size. However, the result of experiments showed that the
input file size was improper to predict the computing resource usage. In this paper, we propose the methodology of
artificial intelligence with considering the properties of GDSII file to handle circuit design files more efficiently. The
conversion time will be optimized by controlling the hardware resource for data conversion as long as the conversion
time is predictable through analyzing the design data. Neural networks are used to predict the conversion time for this
research. In this paper, the application of neural networks for the time prediction will be discussed and experimental
results will be shown with comparing to statistical model based approaches.
Sub Resolution Assist Features (SRAFs) are now the main option for enabling low-k1 photolithograpy. These technical challenges for the 45nm node, along with the insurmountable difficulties in EUV lithography, have driven the semiconductor mask-maker into the low-k1 lithography era under the pressure of ever shrinking feature sizes. Extending lithography towards lower k1 puts a strong demand on the resolution enhancement technique (RET), and better exposure tool. However, current mask making equipments and technologies are facing their limits. Particularly, due to smaller feature size, the critical dimension (CD) linearity of both main cell patterns and SRAFs on a mask is deviated from perfect condition differently. There are certain discrepancies of CD linearity from ideal case. For example, as the CD size gets smaller, the bigger CD discrepancy is to be.
There are many technologies, such as hard-mask process and negative-resist process and so on. One of them is an assist feature correction, which can be applied to achieve better CD control. In other words, in order to compensate this CD linearity deviation, the new correction algorithm with SRAFs is applied in data process flow. In this paper, we will describe in detail the implement of our study and present results on a full 65nm node with experimental data.
As the minimum feature size gets smaller, the use of optical proximity correction (OPC)
becomes more aggressive. The time for mask data preparation dramatically increases.
The increase in the number of small size patterns in design causes the increase of Mask Rule
Check (MRC) error. It brings the need for checking the error between mask fab and Taped-out
customers. Therefore, the Turn-Around Time (TAT) is enlarged.
MRC offers not only the rule check but also the violated-pattern-correction to satisfy the quality
requested by the customers.
In this paper, we suggest a new MRC flow by using new MRC tool that carrys out MRC over
various input of e-beam data and handles the MRC output data.
In case of the violated pattern which approaches Mask Constraint we expand violated pattern
size for pattern correction. And the elimination method can be applied to very small pattern.
We describe how well preformed differently in mask exposure time and inspection capability.
Mask data volume is dramatically increasing by using RET like OPC due to scaling design rule. This has become a burden to MDP and a barrier to TAT. Mask manufacturers have been making various efforts to solve this problem. Although Distribute processing (DP) is one of effective solutions, there remain some limitations: DP needs a lot of CPUs and software license copies, and its management is not efficient at all. Most of well-known mask data preparation (MDP) commercial software require different licenses to each format. Besides, they have no management function to deal with the entire distribute processing system, on account of which user's DP system is not in a fully dynamic state. Those who use commercial MDP software set up their DP system with CPUs fixed by the number of licenses. If user has only one license, this problem does not happen. However, most MDP users have more than one license. If a user wants the DP state which is fully dynamic, he must always consider both the number of licenses and that of available CPUs. This is reason why we have made a DP management server which allocate MDP software to CPUs. It can prevent the loss of CPU time and automate data flow. It's operation is not complicated; effect is powerful. In this paper, we will show advantages in using DP management server and different from other load balance tools.
The low-k1 lithography produces large volumes of mask data resulting in more complex optical proximity effect. It
puts heavy burden on MDP flow and affects turn around time (TAT). To solve this problem, DP (Distributed Processing) method has been introduced. Even though DP is a very powerful tool to reduce the MDP time, there still might be
unexpected pattern drop issue. In order to deal with this issue, the verification step was added in MDP flow. The present
verification method is a boolean operation using 2 machine data after converting as a same way. However this
verification method has two shortcomings. First, this method is not suitable to detect the same error caused by same
software bug. Secondly, it needs double conversion time. A new verification method should be much faster and more
accurate than the current verification method. In this paper, the new verification method will be discussed and
experimental results using the new verification method will be shown with comparing to the old verification method.
As the critical dimension (CD) becomes smaller, various resolution enhancement techniques (RET) are widely adopted. In developing sub-100nm devices, the complexity of optical proximity correction (OPC) is severely increased and applied OPC layers are expanded to non-critical layers. The transformation of designed pattern data by OPC operation causes complexity, which cause runtime overheads to following steps such as mask data preparation (MDP), and collapse of existing design hierarchy. Therefore, many mask shops exploit the distributed computing method in order to reduce the runtime of mask data preparation rather than exploit the design hierarchy. Distributed computing uses a cluster of computers that are connected to local network system. However, there are two things to limit the benefit of the distributing computing method in MDP. First, every sequential MDP job, which uses maximum number of available CPUs, is not efficient compared to parallel MDP job execution due to the input data characteristics. Second, the runtime enhancement over input cost is not sufficient enough since the scalability of fracturing tools is limited. In this paper, we will discuss optimum load balancing environment that is useful in increasing the uptime of distributed computing system by assigning appropriate number of CPUs for each input design data. We will also describe the distributed processing (DP) parameter optimization to obtain maximum throughput in MDP job processing.
In the IC process, the designed circuit pattern is drawn onto film or glass plate as a photo mask. This original mask is used to transform its transparent pattern onto semiconductor wafers by optical projection. To make photo mask we should convert the design data into a format that the e-beam write tool can understand. This MDP (Mask Data Preparation) process is getting more and more complicated to support many kinds of e-beam data format which is required not only for each electron beam writers but die to database inspection tools. It gives us a burden to treat various MDP flow and this may impact on turn around time (TAT). Therefore, it becomes more necessary to make MDP flow simpler by unifying the various mask data formats. Moreover it is required to suppress huge data volume due to design rule shrink and aggressive OPC. To address these issues, the Open Artwork System Interchange Standard (OASISTM) has been approved by the EDA industry and is officially announced by SEMI Data Path Task Force. OASIS data format allows the reduction in file size compared to GDSII while the processing time such as MRC and MDP is not influenced. Also OASIS is effective in reducing complexity of mask data preparation flow. In this paper, the implementation of OASIS format within mask data preparation flow will be discussed and experimental results of OASIS-based data flow will be shown with comparing to traditional GDSII/MEBES-based data flow.
In this paper, the influence of dose modulation on CD trend by using electron beam exposure model has been investigated and simulated. To predict CD trend, we developed an analysis program, which shows the exposed energy profile and the corrected CD distribution in mask. First, it calculates the factor of fogging effect correction (Df) from pattern density distribution with the assumption that fogging effect depends on only pattern density. And then it calculates the modified dose for correcting both proximity and fogging effect. From dose distribution, the corrected CD is calculated analytically by using e-beam lithography model: see Figure 1. It can give a glance how the dose modulation method has an influence on the CD uniformity. Moreover, the result of global error correction such as side, radial error at the mask writing stage has been analyzed in this study.
In this paper, material nonlinear behavior of PZT wafer (3202HD, CTS) under high electric field and tensile stress is experimentally investigated and the nonlinearity of the PZT wafer is numerically simulated. In the simulation, new definitions of the piezoelectric constant and the incremental strain are proposed. Empirical functions that can represent the nonlinear behavior of the PZT wafer have been extracted based on the measured piezo-strain under stress. The functions are implemented in an incremental finite element formulation for material nonlinear analysis. With the new definition of the incremental piezo-strain, the measured nonlinear behavior of the PZT wafer has been accurately reproduced even for high electric field.
A systematic method for the model-based optical proximity correction in presented. This is called optical proximity effect reducing algorithm (OPERA) and has been implemented to TOPO, an in-house program for optical lithography simulations. Comparing simulational results as well as experimental results, we found that OPERA is not only suitable for shape restoration but also for resolution enhancement. However, the resulting optimized patterns have a high degree of complexity and this brought up a number of issues for mask manufacturing. First, data volume and exposure time were dramatically increased for conventional e-beam file formats. This was solved by using the MODE6 format that preserves data hierarchy. Second, due to excessive shot divisions, a variable-shaped beam machine could not finish the exposure process. A raster-scan beam machine successfully finished the exposure. Finally, a die-to-die inspection was performed but many false defects that do not affect wafer printing were defected. This will be solved by a new type of tool that inspects a mask by evaluating its aerial image.