As design rule has decreased, blank type or photo resist, which meets requirement of resolution, has been developed.
HT PSM mainly used to pattern small line width has no longer advantages for immersion wafer process. It makes binary
mask to be gradually used for mask production. Comparing to HT PSM, the production of binary mask has a relatively
simple process. However, we may consider optical density, PR or Cr thickness, etch selectivity, and ID bias related to
linearity for applying binary mask below sub-45nm. In this paper, we will compare and analyze difference between
actual manufacture and theoretical optic level such as optical density. Finally, based on our experiment, optimal
combination of photoresists and blanks which can realize sub-45nm node will be discussed.
Strong resolution enhancement techniques (RETs) are highly demanded to overcome the resolution limit of sub-60nm lithography. ArF immersion lithography may be the best candidate for sub-60nm device patterning. However, the polarization effect becomes more prominent to degrade the image quality in high NA immersion lithography as the feature size shrinks. Therefore, it is important to understand the polarization effect in the mask. The induced polarization effect shows the different aspects between the binary and the attenuated phase shift mask (PSM). In this paper, we considered the effects of polarization state as a function of mask properties. We evaluated the performances of the binary mask and the attenuated PSM by using simulation, AIMS<sup>TM</sup> (Aerial Image Measurement System) tool, and real wafer printing. We find out that there are no differences between the binary mask and the attenuated PSM in view of image contrast and mask error enhancement factor (MEEF).
Chemically amplified resist materials are now available to reach critical dimensions of the pattern close to 32 nm values.
Pattern collapse is a very serious problem in fine patterning less than 32 nm critical dimension, because it decreases the
yield. The pattern collapse is the pattern response to unbalanced capillary forces acting on the pattern walls during the
spinning drying step after development process. Centrifugal force has not considered for pattern collapse modeling up to
now, so that pattern collapse due to spinning is studied. In this study we investigate the 32 nm node pattern collapse
mechanism with radial distance and rinse speed of dense patterns. In the process of creating the simulation tool, the
rotating model is used. As rinse speed and radial distance are increased, critical aspect ratio is decreased. As a result,
pattern collapse is increased.
Each generation of semiconductor device technology drives many new and interesting resolution enhancement technologies (RET). As minimum feature size of semiconductor devices have shrunk, the exposure wavelength has also progressively shrunk. The 193 nm lithography for low-k<sub>1</sub> process has increased the appearance of progressive defects on masks often known as haze or crystal growth. Crystal growth on a mask surface has become an increasing issue as the industry has adopted a 193 nm wavelength in order to increase lithographic resolution and print ever decreasing device line width. Haze is known to be a growing defect on photomask as a result of increased wafer lithography exposure and photochemical reactions induced by combination of chemical residuals on the mask surface. We build experimental system to create and detect the haze growth. A photomask is enclosed in a glove box where the atmosphere and exposure conditions are controlled and monitored throughout the exposure processing. A test photomask is exposed to accumulate the dose of laser radiation. And then spectroscopic ellipsometry and metallographic microscope techniques are used to check the surface conditions of the masks before and after the laser exposure. We found that spectroscopic ellipsometry measurement values of Δ and Ψ were changed. The results of the spectroscopic ellipsometry analysis show the change of the haze thickness on mask surface. Thickness and roughness of the mask surface is increased with the exposure. This means that haze grows on the mask surface by the exposure. Masks become useless due to transmission loss or defect generation, which is directly related to the formation of the haze. The haze causes the increase of mask thickness, transmission drop and affects the formation of pattern. So, we investigated the linewidth variation and the process window as a function of haze size effect with Solid-E of Sigma-C.
Resolution enhancement technology (RET) refer to techniques that extend the usable resolution of an imaging system without decreasing the wavelength of light or increasing the numerical aperture (NA) of the imaging tool. Off-axis illumination (OAI) and phase shift mask (PSM) are essentially accompanied with optical proximity correction (OPC) for most devices nowadays. In general, these three techniques do not work in isolation and the most aggressive mainstream lithography approaches use combinations of all RETs. In fact, OAI and PSM are essentially useless for typical chip-manufacturing applications unless accompanied by OPC. For low k<sub>1</sub> imaging, strong OAI such as Quasar or dipole illumination types is the best. We used dipole illumination in this study. By using strong OAI, the amplitude of the 0<sup>th</sup> order is decreased and the amplitude of the 1<sup>st</sup> order is increased. Chromeless phase lithography (CPL) is one of PSM technologies and CPL mask is the possible solution for small geometry with low mask error enhancement factor (MEEF). CPL uses only 180 degrees phase-shifter on transparent glass without chromium film to define light-shielding region, destructive interference between light transmitted through the 0 degree and 180 degrees regions produces dark images. To obtain the best resolution, proper OPC is required with CPL. While the most common and straightforward application of OPC is to simply move absorber edges on the mask by giving simple mask bias, the interesting and important additional technique is the use of scattering bars. Also, we can use zebra patterns for the transmission control. Mask intensity transmission changes can impact the image quality. Zebra patterns are formed by adding chromium transverse features. The transmission will be controlled by the zebra pattern density. Technology node with ArF source is studied and the mask optimization is found to be a critical. And the linewidth of scattering bars, transmission (using zebra feature) are varied at line and space (L/S) patterns. We used 65 nm node 5 L/S and 45 nm node isolated line pattern. In order to optimize the zebra pattern density, we need to control the line width and pitch of the zebra patterns. For dense line and isolated line, the use of scattering bars and zebra patterns affected target critical dimension. We found out the better process window at dense 65 nm node by comparing the use of scattering bars with zebra patterns. Likewise, we optimized the isolated 45 nm node.
Haze formation on reticle continues to be a significant problem for the semiconductor industry. Haze can be formed on the outside pellicle and on the quartz back side of the reticle. Major component of the haze is known to be aluminum sulfate that comes from the reticle cleaning process. The reticle materials, the exposure wavelength, roughness of photomask and this haze will affect the resolution and process latitude. So the haze on the mask surface becomes more important. We need to know the usable lifetime of the reticle in terms of haze and need to know how to increase the
lifetime by removing the haze, if possible. This paper introduces the haze measurement method by using the spectroscopic ellipsometry. The quantity of the haze including the roughness of the reticle can be accurately measured by the spectroscopic ellipsometry. The spectroscopic data shows the increase of the delta value with the energy dose given to the reticle. We confirm that this signal increase is directly the result of the haze increase with dose.
The mask error enhancement factor (MEEF) minimization is much emphasized due to the reduction of the device technology node. The MEEF is defined as how mask critical dimension (CD) errors are translated into wafer CD errors. We found that the pattern density had influenced the MEEF and the MEEF changed with the pattern density variation. We also tried to obtain the 90 nm CD value with optimized diffusion length of the chemically amplified resist. It turned out that a very small diffusion length should be used to get the desired 90 nm line width with 193 nm. We used line and space (L/S) dense bars, 3 L/S bars only and isolated line pattern for the pattern density dependency and to obtain different MEEFs. In order to determine the MEEF by the various pattern densities, a commercial simulation tool, Solid-E, was used. We could obtain the minimum MEEF values for the different pattern densities by using this procedure.
As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k<sub>1</sub> has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSM's. For the low-k<sub>1</sub> lithography, we have researched CLM technique as a good solution especially for sub-65nm node.
As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with pattern's pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field.
We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer.
Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.
In the ArF lithography for sub-100nm, PSM (Phase Shift Mask) has been considered as one of the basic RETs (Resolution Enhancement Techniques). Nowadays, besides attenuated PSM, alternating PSM and CPL (Chromeless Phase Lithography) containing Cr patch is widely studied for targeting sub-100nm. Since 2nd process using 365nm laser tools for Cr patch has been a wide gap between the reality and the demands, various candidates using 254nm laser or e-beam exposure tool have been presented to overcome the current 2nd process limitation. And, the Cr patch operate as an assist pattern to control the transmittance of mask, therefore, the CPL mask with Cr patch have advantages of improving process margin such as dose margin and its applicable flexibility for various layers, dense or isolated pattern in the memory and logic device. In this paper, we scrutinize the feasibility of 2nd alignment using 10keV e-beam. Process issues such as the charging effects caused by 2nd e-beam exposure on the 1st Cr etched substrate were evaluated as well.
High speed circuit usually requires additional gate scaling regardless of its developed technology node. In this paper, we demonstrate the full-chip-level wafer result for 100nm node SRAM gate and the possibility of future gate scaling. Test reticle is manufactured using chromeless phase lithography(CPL). CPL technology uses a COG that consists of p -phased-etched quartz and chrome shield for various gate CD formation. Critical transistor area is 100% transmission PSM. However, less-critical area should be a chrome for adequate CD control. Because light interference is weakened in phase area according to the separation of paired phase edges increase. The optical performance and manufacturing issues of CPL are evaluated compared to other PSM technologies. Finally, we describe how to optimize the CPL mask using simulation and wafer analysis to obtain the acceptable OCV and DOF margin for volume production.
The finite-difference time-domain (FDTD) is a standard method for simulating mask topography effects. Its algorithm is simple, robust, and easy to implement. However, the FDTD algorithm consumes a lot of computer memory and time. For full three-dimensional simulation of a small contact pattern, it takes several hours on a personal computer. To reduce computing time, we adopted the differential method (DM) which solves the Maxwell equations in spatial frequency domain. Speed is the main advantage of DM over FDTD. To verify the numerical accuracy of DM, we compared the aerial images of several line/space patterns whose topography effects are predicted by DM and FDTD. For the calculation of the aerial images, we used a vector model. For unpolarized light, the maximum intensities differ by about 7%. Having assessed the accuracy of DM, we now describe the simulation result of a two-dimensional pattern. The pattern mainly contains densely packed rectangles. The size of the simulation domain was taken to be 1.972 μm × 4.368 μm × 0.350μm on the mask scale where the first two numbers represent the size of the unit cell of the pattern. Illumination condition is KrF source, annular aperture of 0.85/0.55, and NA of 0.7. Estimated running time of FDTD for topography simulation was 180 days. However, DM took about 280 minutes. The resulting aerial image agreed within about 8% with an experimental image directly measured by an AIMS-FAB.
Alternating phase shift mask (AltPSM) is considered as one of the most promising technique in leading-edge lithography. Its optical performance can be verified by sub-100nm gate generation and guaranteed device properties, indicated as depth of focus (DOF) and on chip CD variation (OCV). Nevertheless, continuous gate reduction in logic device demands more high-qualified mask process and optimization of illumination to overcome resolution limit. As one of the solution, appropriate mask structure and OPC rule dependent on illumination condition are evaluated. Issues out of mask manufacturing and Cr-less PEPSM as substitution of PEPSM are also discussed. Besides, interrelation between issues of mask and optical characteristics are investigated and compared mutually. In the end of this paper, we propose the optimum mask type and opportune time for ArF lithography.
Chrome Less phase lithography (CPL) may be the crucial technology to print 100nm node and below. CPL can apply to various design layers without causing phase conflicts, while phase edge phase shift mask (PEPSM) is beneficial for specific pattern configurations and pitches. Therefore, we tested the feasibility of CPL including phase grating and hybrid CPL. And we tested the two types of CPL such as mesa and trench structures to decide the proper shifter forming method. We evaluated pattern fidelity of CPL using simulation, aerial image measurement system (AIMS) and wafer printing. Finally, we will compare the optical performance between CPL and PEPSM for 100nm node SRAM gate.
As high-speed non-memory devices require narrow gate widths of less than 100 nm, the technology for this requirement shou7ld be guaranteed. In view of microlithography, one candidate to support such a narrow gate width is a phase edge (PE) PSM technique. However, because this PEPSM technique has not yet been thoroughly developed in the viewpoint of mask making, an activity to find optimal mask parameters for best optical performances should be made. In this paper, optical performances of PEPSM have been described under various geometrical structures and phase defects as mask parameters. Optical performances of PEPSM were strongly dependent on the pattern pitch, the optimal phase, and the mask structure. From our studies, the optimal phase of shifter was considered to be 179 degrees and the optimal mask structure expressed in dry/wet etch ratio was 50/130 degrees when considering the overall pitch. The phase defect having its phase of less than 50 percent did not seriously affect the lithography patterning. We could easily make PEPSMs having maximum phase defects of 50 degrees with our hybrid etch process. Finally, we could build the manufacturing process of PEPSM for sub-100 nm resist CD patterning.