Currently, we are supplying defect-free EUV mask for device development. This was one of the biggest challenges in the implementation of EUV lithography for high volume manufacturing (HVM). It became possible to hide all multi-layer defects by using defect avoidance technique through improvement of blank mask defectivity and development of actinic blank inspection tool. In addition, EUV pellicle is also considered as a requisite to guarantee predictable yield. Both development of mask shop tools and preparation of EUV scanner for pellicle are going well. However, still membrane needs to be much improved in terms of transmittance and robustness for HVM. At the conference, EUV mask readiness for HVM will be discussed including blank defect improvement, preparation of actinic tools and pellicle development.
Achieving lithographic printability at advanced nodes (14nm and beyond) can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. Early identifying of yield-limiter hotspots is essential for both foundries and designers to significantly improve process maturity. A real challenge is to scan the design space to identify hotspots, and decide the proper course of action regarding each hotspot. Building a scored pattern library with real candidates for hotspots for both foundries and designers is of great value. Foundries are looking for the most used patterns to optimize their technology for and identify patterns that should be forbidden, while designers are looking for the patterns that are sensitive to their neighboring context to perform lithographic simulation with their context to decide if they are hotspots or not. In this paper we propose a framework to data mine designs to obtain set of representative patterns of each design, our aim is to sample the designs at locations that can be potential yield limiting. Though our aim is to keep the total number of patterns as small as possible to limit the complexity, still the designer is free to generate layouts results in several million of patterns that define the whole design space. In order to handle the large number of patterns that represent the design building block constructs, we need to prioritize the patterns according to their importance. The proposed pattern classification methodology depends on giving scores to each pattern according to the severity of hotspots they cause, the probability of their presence in the design and the likelihood of causing a hotspot. The paper also shows how the scoring scheme helps foundries to optimize their master pattern libraries and priorities their efforts in 14nm technology and beyond. Moreover, the paper demonstrates how the hotspot scoring helps in improving the runtime of lithographic simulation verification by identifying which patterns need to be optimized to correctly describe candidate hotspots, so that only potential problematic patterns are simulated.
As a photomask feature size shrinks, chrome (Cr) dry etching process is one of the most critical steps which define the
performance of critical dimensions (CDs). In consequence, plasma conditions should be maintained stable in a etch
In this work, advanced methodologies using plasma monitoring tools are introduced; Optical Emission Spectroscopy
(OES) and the Self-Excited Electron Resonance Spectroscopy (SEERS). After an etch chamber was monitored with these
tools, plasma conditions could be categorized with respect to the three parameters; the spectra, the electron collision rate,
and the electron density distributions.
Finally, it is possible to predict the CD performance of the chamber by checking the specific plasma parameters.
As design rule has decreased, blank type or photo resist, which meets requirement of resolution, has been developed.
HT PSM mainly used to pattern small line width has no longer advantages for immersion wafer process. It makes binary
mask to be gradually used for mask production. Comparing to HT PSM, the production of binary mask has a relatively
simple process. However, we may consider optical density, PR or Cr thickness, etch selectivity, and ID bias related to
linearity for applying binary mask below sub-45nm. In this paper, we will compare and analyze difference between
actual manufacture and theoretical optic level such as optical density. Finally, based on our experiment, optimal
combination of photoresists and blanks which can realize sub-45nm node will be discussed.
A photomask dry etch process typically uses chlorine and oxygen plasma for chrome etching with resist masking. This gas mixture leads macro- and micro-loading as different pattern density with mask-to-mask and within a mask. Thus, there have been several approaches to reduce chrome etch loading by changing etch chemistry, etch conditions and mask materials. Using hard mask material on the chrome layer can minimize chrome etch loading and reduce chrome etch bias. In this paper, chrome etch characteristics which use hard mask materials is investigated.
Phase Shift Masks (PSMs) have been widely used in the photomask industry for nowadays. Among several types of PSMs, Alternating Aperture PSM (AAPSM) allows for better resolution within other advantages. This paper deals with micro-trench formation during quartz etching. Micro-trench can produce distortion of the light intensity and lead unwanted results on wafer. Several experiments are performed with respective etch conditions; fluorine (F) gas species, gas flow rates, bias powers, and substrate temperatures while other conditions are fixed. Quartz etching is processed with Inductively Coupled Plasma (ICP) system. Etched morphologies are observed by Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM), and a surface profiler to select the best condition as functions of etch parameters. Results show that bias power is the most important factors to decide quartz surface morphologies. Finally, mask image is simulated by AIMS system under given condition.