A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an
introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage
down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic
manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop
process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to
define critical layers with double photolithography and etch process becomes increasingly evident.
Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D
features is so challenging that opposing line-ends can only be defined using an additional litho and etch
step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit.
Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning
technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and
then successfully decomposed, so an additional set of restrictions is required to make layouts double
patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that
they can be patterned using both masks. The electric performance of this cut circuitry may be highly
dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to
misalignment between the two patterning steps. We used representative logic layouts of metal level and
realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend
splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink
approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of
parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned
using double patterning aware OPC and printability verification tools.
A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising
solutions by maximizing the common process window. However, process window improvement of the pixel-based
SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask
rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production
without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to
process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by
balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm
device node development was proposed to keep the mask complexity low and to take full advantage of process window
improvement using pixel-base SRAF insertion.
Metal layers have some drawbacks in building up model based OPC (MBOPC) because metal layers are mainly
composed of 2 dimensional (2D) patterns which show modeling inaccuracy and the difficulty of fragment optimization
compared with 1-dimensional patterns. As a result, metal layers have considerable hot spots such as pinch, bridge and
insufficient contact overlap. The modeling inaccuracy of 2D patterns results from a few reasons like measurement noise,
inaccurate optical simulation and empirical resist modeling etc. The fragment optimization operated by rule does not
control automatically corner rounding problems induced by small jogs of 2D patterns. The design for manufacturability
(DFM) is known to provide a solution to overcome these problems. One of engines operating the DFM is MBOPC,
which is made by an empirical process model and offers the process variation counter map simulated by the MBOPC
engine. However, the accuracy of the simulation is quite low because we cannot avoid over-corrected patterns generated
inevitably with the empirical model. In order to detect and correct the hot spots caused by the design itself, that is, the
inherent function of the DFM, it is necessary to provide the OPC engine of the physical model with the optimized
illumination condition to rule out empirical effect. Physical model is more emphasized in case of process window
simulation because of its accuracy in the edge boundary of process window. One of important function of DFM for the
metal layers is to enhance the contact overlap margin which can be influenced by the lithography process such as line
end shortening, corner rounding effect and miss-alignment. Etch process is also a significant parameter of contact
overlap. Calibrated process model is very effective to detect the insufficient contact overlap with process window.
In this paper, MBOPC of sub-45nm node metal layers is studied to provide the effective DFM engine. The DFM flow
with renewed MBOPC engine will show the improved process window and large contact overlap margin and will also
make it possible to search and correct just patterns capable of decreasing the process window by only layout defect itself.
The OPC model is very critical in the sub 45nm device because the Critical Dimension Uniformity (CDU) is so tight to
meet the device performance and the process window latitude for the production level. The OPC model is generally
composed of an optical model and a resist model. Each of them has physical terms to be calculated without any wafer
data and empirical terms to be fitted with real wafer data to make the optical modeling and the resist modeling. Empirical
terms are usually related to the OPC accuracy, but are likely to be overestimated with the wafer data and so those terms
can deteriorate OPC stability in case of being overestimated by a small cost function.
Several physical terms have been used with ideal value in the optical property and even weren't be considered because
those parameters didn't give a critical impact on the OPC accuracy, but these parameters become necessary to be applied
to the OPC modeling at the low k1 process. Currently, real optic parameter instead of ideal optical parameter like the
laser bandwidth, source map, pupil polarization including the phase and intensity difference start to be measured and
those real measured value are used for the OPC modeling. These measured values can improve the model accuracy and
stability. In the other hand these parameters can make the OPC model to overcorrect the process proximity errors without
The laser bandwidth, source map, pupil polarization, and focus centering for the optical modeling are analyzed and the
sample data weight scheme and resist model terms are investigated, too. The image blurring by actual laser bandwidth in
the exposure system is modeled and the modeling result shows that the extraction of the 2D patterns is necessary to get a
reasonable result due to the 2D patterns' measurement noise in the SEM. The source map data from the exposure
machine shows lots of horizontal and vertical intensity difference and this phenomenon must come from the
measurement noise because this huge intensity difference can't be caused by the scanner system with respect to the X-Y
intensity difference specification in the scanner. Therefore this source map should be well organized for the OPC
modeling and a manipulated source map improves the horizontal and vertical mask bias and even OPC convergence. The
focus parameter which is critical for the process window OPC and ORC should be matched to the tilted Bossung plot
which is caused by uncorrectable aberration to predict the CD change in the through focus with a new devised method.
Pupil polarization data can be applied into the OPC modeling and this parameter is also used for the unpolarized source
and the polarized source and specially this parameter helps Apodization loss to be 0 and is evaluated for the effect into
With the analysis and optimization about the model parameters the robust model is achieved in the sub 45nm device
As the minimum pitch size becomes smaller, the gate-poly critical dimension uniformity (CDU) is a critical parameter for the device performance and an important indicator of the OPC capability. From the photolithographic point of view, the root causes of increasing gate-poly CDU is due to corner rounding effects, ripples, misalignment between the gate-poly and active layers. The corner rounding effect of the gate-poly region on the active can be severe for the sub L50 device because the space between the active layer and the gate-poly layer becomes narrow.
To correct these effects caused by litho-process the advanced OPC technique and the design rule limitation should be optimized. The OPC method which can be used to improve gate-poly CDU is defined as "Litho Process-aware OPC for the Gate-Poly CDU improvement" in this paper. The pixel based simulation algorithm which gives lots of information compared to the sparse simulation algorithm is used for the OPC and ORC. The design rule for the space limitation from RX to PC is evaluated with its own litho-process model and this evaluation result has to be reflected to the design rule and the OPC recipe to manipulate the polygons is also necessary. Additionally if misalignment exists in the minimum space between the active layer and gate-poly layer during the photo process, this corner rounding effect can be more serious, so this misalignment accounted to reduce the corner rounding effect on the gate-poly CDU. The redundant field poly polygon enclosing the contact can be cut by keeping the design rule for the overlap margin between the poly layer and the contact layer. The miss-alignment effect can be considered indirectly by sizing the active layer. The OPC convergence technique is also used to reduce the ripple phenomenon close to the concave corner and line end. As a result of retargeting to accommodate a corner rounding effects, ripple effects and misalignment correction led to an improved gate-poly CDU for a sub-50nm device.
Sub-resolution assist features (SRAFs) have been used to enhance lithographic process window of main features. As the device is scaled down, the SRAF size decreases drastically and the distance between main features and SRAF closes up. The variation of main feature CD and SRAF size from mask production process influences destructively on gate CD control and it makes the device performance degraded. Fabrication of small and uniform-sized SRAFs is one of the key mask technologies because mean-to-target (MTT) and CD uniformity of SRAFs are more difficult to be controlled than those of main features. In addition, for sub-50 nm design nodes, mask topography effects can not be neglected because exposure wavelength is similar to a mask pitch from main feature to SRAF or SRAF to SRAF. In order to consider mask topography effects, all lithographic simulations were performed with a rigorous coupled wave analysis (RCWA) electromagnetic field calculation.
In this study, we will demonstrate that SRAF size tolerance is deduced from the effects of SRAF size deviation from the mask production on a main feature CD. To define the SRAF size deviation effects, main feature CD variation is simulated for different SRAF sizes. We will explore SRAF size tolerances for sub-50 nm design nodes. It can be suggested as one of the mask requirements.
Since the sub-50nm logic lithography approaches to k1 value of 0.3, it seems to be an impossible task to print typical
logic patterns composed of random shapes and mixed pitches using the conventional resolution enhancement technology
(RET). As one of the effective solutions to deal well with this issue, lithography friendly design (LFD) and advanced
optical proximity correction (OPC) technology have been considered and developed. However, the investigation on the
distortion types of various 2-dimensional patterns has rarely been preceded up to now, while lithographical hot spots are
observed are dominated by the 2-dimensional patterns rather than in the 1-dimensional patterns. In order to provide a
LFD layout and a good OPC performance for the future node logic device, the analysis and the hot spot's classification
of the 2-dimensional pattern need to be performed. Based on our analysis of various pattern types at mimic-logic test
block, a feedback strategy was implemented to reduce the 2-dimensional hot spots through the correction stage of the
OPC recipes. In our study, we find out the proper value of ground rule and the cost-effective methodology which should
go with reciprocal encouragement in OPC and LFD. This will give us a good methodology for the lithography
technology nodes and upstream design for manufacturability (DFM) approaches.
We investigated the effect of surfactant-added rinse and soft bake conditions on the pattern collapse in sub-100nm ArF lithography. Pattern collapse was estimated by comparing the critical dimension (CD) and the frequency at which collapse occurred. Collapse could be improved by using surfactant solutions, but the extent was different from the model study concerning the contact angle and surface tension at equilibrium state only. From dynamic surface tension data, we found that surface tension in dynamic mode was more important than that in static mode when spin drying method was used. During the study we found that pattern collapse occurred much easily at the edge of wafer. By increasing bake time or temperature after resist coating, we could decrease the positional difference in the pattern collapse. It is supposed that these results come from the relaxation of internal stress in resist during spin coating
The advent of 193nm ArF lithography opened new era of sub-90nm patterning in DRAM industry. ArF lithography in single layer scheme, however, has limitation in the substrate fabrication of sub-90nm L/S due to the decreased physical thickness of resist less that 3000Å and soft chemical structure of resist. Bilayer scheme, composed of Si-containing top PR and thick organic bottom layer, is gaining attention for its capability of patterning and control of resist thickness as a substitute for single layer. Several resists were evaluated for bilayer process in terms of photo patterning, dry development, bottom PR durability and SEM shrinkage. Resolution down to 80nm was achieved with Si content in the range of 8-9%. Etch selectivity in the dry development was a strong function of Si content and chemical structure of tope PR with pitch size dependence based on O<sub>2</sub>/N<sub>2</sub> gas chemistry in dual frequency plasma tool. Profile control after dry development was subject to change depending on the gas ration (O<sub>2</sub>/N<sub>2</sub>) and power. Resist structure was proved to be a key factor in bottom PR durability at the substrate etch condition. Best combination of top and bottom resists in bilayer scheme will be discussed.
It is expected that ArF lithography will be introduced for device manufacturing for sub-100 nm nodes, as high NA ArF step and scan systems (NA=0.75) become available. We previously reported on a platform, based on a vinyl ether- maleic anhydride (VEMA) alternating polymer system. This platform demonstrated both good resolution and high dry etch resistance in comparison to other platforms based on acrylate and cyclic-olefin-maleic anhydride (COMA) polymer systems. The VEMA platform has been continuously improved to meet the increasing requirements, such as resolution, depth of focus (DOF) iso-dense bias, and post-etch roughness for real device manufacturing. This VEMA system is being implemented for sub-100 nm device with high NA (NA=0.75) ArF exposure systems. In this paper, recent experimental results are reviewed.
A vapor phase silylation process after wet development allows a patterned resist film to have etch resistance similar to that of bi-layer resist. In our study, the mixture of dimethylsilyldimethylamine(DMSDMA) and bis(dimethylamino)methylsilane(B(DMA)MS) was used as a silylation agent. DMSDMA was an effective silylation agent providing silicon compound quickly into resist film and also, had a role of improving the line edge roughness (LER) of resist pattern profile. Bi(DMA)MS, was added as a cross linker to prevent the resist flow due to the drop of glass transition temperature(Tg) of the resist film during silylation. Thermally stable silylated resist pattern was baked at 160 degree(s)C in order to control critical dimension(CD) bias generated by volume expansion during silylation, without desilylation arising at the typical silylation process using DMSMA.
ArF lithography, in combination with chemically amplified resists, has been investigated as one of the most promising technologies for producing patterns below 100 nm. In considering the polymer matrix for 193 nm photoresist applications, factors such as sensitivity, transparency to 193 nm radiation, adhesion to substrate, dry etch resistance, ease of synthesis, and availability of monomers are very critical. In these respects, remarkable progress has been made in development of ArF resist material. Polymers of acrylic and methacrylic esters show good imaging performance at 193 nm, but have insufficient dry-etch resistance under oxide or nitride etch condition. On the other hand, cyclic olefin-maleic anhydride (COMA) alternating copolymers exhibit good dry etch resistance, but have poor resolution capability. We previously reported a new platform, based on a vinyl ether-maleic anhydride (VEMA) alternating polymer system, that demonstrated both good resolution and high dry etch resistance. In this paper, VEMA systems with improved lithographic performance are presented. The new platform (VEMA) showed good performance in resolution, depth of focus (DOF), iso-dense bias, and post-etch roughness. With conventional illumination (NA=0.6, sigma=0.7), 120 nm dense line/space patterns with 0.4 (mu) M DOF were resolved. And 90 nm L/S patterns 0.6 (mu) M DOF were resolved with off-axis illumination (NA=0.63). Another important factor to be considered for the dry-etch process is post-etch roughness. In the case of VEMA system a clean surface was observed after etch under oxide, nitride, and poly conditions. The VEMA resist system is regarded as one of the most production-worthy material for real device manufacture.
In this work we have studied new types of olefin-containing alicyclic lactones such as (alpha) -angelicalactone(AGL), (gamma) -methylene- (gamma) -butyrolactone((gamma) -MBL), (alpha) -methylene- (gamma) -butyrolactone((alpha) -MBL) and their derivatives. Particular attention was given to (alpha) -BML derivatives, which are readily synthesized. The relative monomer reactivities of the various lactones were found to be quite different. However in the case of (alpha) -MBL and its derivatives they have good radical reactivities with methacrylates and maleic anhydride. Methacrylate derivatives with acid-labile protecting groups were introduced for dissolution contrast. To further promote adhesion the relative ratios of maleic anhydride and norbornylene derivatives was optimized. These novel resists resolve 120nm L/S with conventional illumination (NA=0.6, (sigma) =0.7) and 0.6micrometers DOF with annular illumination (NA=0.6, (sigma) $=0.6/0.8). And also 100nm L/S resolution was achieved using strong off-axis illumination. Oxide etch resistance was found to be equivalent to acetal based KrF resists. Post exposure delay (PED) stability of more than 1 hour was achieved.
In this paper we analyze the effect of mask reduction ratio in alternating phase shift masks. To properly predict image imbalance for different reduction ratios, a topography simulator was used. As the mask reduction ratio is increased, the aerial image imbalance is improved. As the reduction ratio is decreased, the amount of undercutting to compensate for the difference of image imbalance is increased. For undercut margins with lOOnm line/space patterns, 4X reduction has about ± 200 A of undercut margins, while 6X and 10X have about ± 300 A. The phase margin for 120 nm line/space patterns is about ± 1.5° regardless of reduction ratios. As the mask reduction ratio is varied, the optimum phase is shifted to keep the aerial image displacement constant through focus.