As the technology node shrinks, ArF Immersion reaches the limitation of wafer patterning, furthermore weak point during the mask processing is generated easily. In order to make strong patterning result, the design house conducts lithography rule checking (LRC). Despite LRC processing, we found the weak point at the verification stage of optical proximity correction (OPC). It is called the hot spot point (HSP). In order to fix the HSP, many studies have been performed. One of the most general hot spot fixing (HSF) methods is that the modification bias which consists of “Line-Resizing” and “Space-Resizing”. In addition to the general rule biasing method, resolution enhancement techniques (RET) which includes the inverse lithography technology (ILT) and model based assist feature (MBAF) have been adapted to remove the hot spot and to maximize the process window. If HSP is found during OPC verification stage, various HSF methods can be applied. However, HSF process added on regular OPC procedure makes OPC turn-around time (TAT) increased. <p> </p>In this paper, we introduce a new HSF method that is able to make OPC TAT shorter than the common HSF method. The new HSF method consists of two concepts. The first one is that OPC target point is controlled to fix HSP. Here, the target point should be moved to optimum position at where the edge placement error (EPE) can be 0 at critical points. Many parameters such as a model accuracy or an OPC recipe become the cause of larger EPE. The second one includes controlling of model offset error through target point adjustment. Figure 1 shows the case EPE is not 0. It means that the simulation contour was not targeted well after OPC process. On the other hand, Figure 2 shows the target point is moved -2.5nm by using target point control function. As a result, simulation contour is matched to the original layout. This function can be powerfully adapted to OPC procedure of memory and logic devices.
In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches
to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning
technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both
stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In
terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal
lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process
stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x
nm hole patterning process using double patterning technology combined with negative tone development (NTD).
Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD
with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be
discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through
NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be
As design rules shrink, Critical Dimension Uniformity (CDU) and Line Edge Roughness (LER) have a dramatic
effect on printed final lines and hence the need to control these parameters increases. Sources of CDU and LER
variations include scanner auto-focus accuracy and stability, layer stack thickness, composition variations, and
exposure variations. Process variations, in advanced VLSI production designs, specifically in memory devices,
attributed to CDU and LER affect cell-to-cell parametric variations. These variations significantly impact device
performance and die yield.
Traditionally, measurements of LER are performed by CD-SEM or OCD metrology tools. Typically, these measurements require a relatively long time to set and cover only selected points of wafer area.
In this paper we present the results of a collaborative work of the Process Diagnostic & Control Business Unit of
Applied Materials and Hynix Semiconductor Inc. on the implementation of a complementary method to the CDSEM
and OCD tools, to monitor defect density and post litho develop CDU and LER on production wafers. The
method, referred to as Process Variation Monitoring (PVM) is based on measuring variations in the scattered light
from periodic structures. The application is demonstrated using Applied Materials DUV bright field (BF) wafer
inspection tool under optimized illumination and collection conditions. The UVision<sup>TM</sup> has already passed a
successful feasibility study on DRAM products with 66nm and 54nm design rules. The tool has shown high
sensitivity to variations across an FEM wafer in both exposure and focus axes. In this article we show how PVM can
help detection of Field to Field variations on DRAM wafers with 44nm design rule during normal production run.
The complex die layout and the shrink in cell dimensions require high sensitivity to local variations within Dies or
Fields. During normal scan of production wafers local Process variations are translated into GL (Grey Level) values,
that later are grouped together to generate Process Variation Map and Field stack throughout the entire wafer.
Each generation of semiconductor device technology drives many new and interesting resolution enhancement technologies (RET). As minimum feature size of semiconductor devices have shrunk, the exposure wavelength has also progressively shrunk. The 193 nm lithography for low-k<sub>1</sub> process has increased the appearance of progressive defects on masks often known as haze or crystal growth. Crystal growth on a mask surface has become an increasing issue as the industry has adopted a 193 nm wavelength in order to increase lithographic resolution and print ever decreasing device line width. Haze is known to be a growing defect on photomask as a result of increased wafer lithography exposure and photochemical reactions induced by combination of chemical residuals on the mask surface. We build experimental system to create and detect the haze growth. A photomask is enclosed in a glove box where the atmosphere and exposure conditions are controlled and monitored throughout the exposure processing. A test photomask is exposed to accumulate the dose of laser radiation. And then spectroscopic ellipsometry and metallographic microscope techniques are used to check the surface conditions of the masks before and after the laser exposure. We found that spectroscopic ellipsometry measurement values of Δ and Ψ were changed. The results of the spectroscopic ellipsometry analysis show the change of the haze thickness on mask surface. Thickness and roughness of the mask surface is increased with the exposure. This means that haze grows on the mask surface by the exposure. Masks become useless due to transmission loss or defect generation, which is directly related to the formation of the haze. The haze causes the increase of mask thickness, transmission drop and affects the formation of pattern. So, we investigated the linewidth variation and the process window as a function of haze size effect with Solid-E of Sigma-C.
Recently, a pattern size gradually has reduced to enhance the integration of semiconductor device. As minimum linewidths have shrunk, the exposure wavelength has also progressively shrunk. The exposure wavelengths have been reduced progressively from 436 nm to 365 nm to 248 nm to 193 nm. Expose wavelength shrink caused some serious problems. One of the problems to be solved is growing defect in the reticle during the process. Reticle growing defect is called a haze. Haze is formed around the pellicle, on the quartz side of the mask and on the chrome side of the mask. In this investigation, mask haze is intentionally formed on the backside of mask by 193 nm laser irradiation. And the thickness is measured by the spectroscopic ellipsometry. This paper describes the relationship between transmittance and the haze formation, photochemical reactions and the haze effect on the process latitude. In addition, throughput is decreased due to haze formation.
Haze formation on reticle continues to be a significant problem for the semiconductor industry. Haze can be formed on the outside pellicle and on the quartz back side of the reticle. Major component of the haze is known to be aluminum sulfate that comes from the reticle cleaning process. The reticle materials, the exposure wavelength, roughness of photomask and this haze will affect the resolution and process latitude. So the haze on the mask surface becomes more important. We need to know the usable lifetime of the reticle in terms of haze and need to know how to increase the
lifetime by removing the haze, if possible. This paper introduces the haze measurement method by using the spectroscopic ellipsometry. The quantity of the haze including the roughness of the reticle can be accurately measured by the spectroscopic ellipsometry. The spectroscopic data shows the increase of the delta value with the energy dose given to the reticle. We confirm that this signal increase is directly the result of the haze increase with dose.