This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node
DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation)
control become more important to meet the performance goal for high speed in DRAM. The main factors which
influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is
required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied
new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of
interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density
difference between spider mask and real gate mask, the skew difference occurs between them. We tested the
effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10
mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the
ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm).
This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in
real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch
skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce
this skew difference between spider mask and real mask, we applied open field mask correction term and long
range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy
of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up
It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC
for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh
thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention
as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse
solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including:
DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process
window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask.
Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors
responsible for their differences include composition of the cost function that is minimized, constraints applied during
optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In
this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom
for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be
manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can
control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized
lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.
For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement
techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a
portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being
relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be
used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the
The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult
portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC
corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined
runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.
Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks
provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the
leading candidates for low-k1 lithography, one major task to overcome is mask manufacturability including mask data
fracturing, MRC constraints, writing time, and inspection. In prior publications<sup>[4,5]</sup>, it has been shown that the Inverse
Synthesizer (IS<sup>TM</sup>) product has the capability to adjust for mask complexity to make it more manufacturable while
maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been
demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to
further reduce ILT mask complexity without compromising too much of process window. These areas include flexible
controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of
main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these
approaches on e-beam mask writing time and lithography performance is presented in the paper.
Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks
provide significantly better litho performance and need to be enabled for production as one of the leading candidates for
low-k1 lithography. By the very nature ILT masks are computed, they could seem to be complicated to manufacture in
production. In a prior publication , it has been shown at clip level that the Inverse Synthesizer (IS<sup>TM</sup>) product has the
capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of
nearly ideal ILT mask. The production readiness of ILT needs to be studied at full chip level with various aspects
including mask data fracturing, MRC constraints, writing time, and inspection.
The computation of ILT mask usually starts with the calculation of an optimized contoured mask then followed by
manhattanization step to convert contour into horizontal-vertical segments. By varying the segmentation length during
manhattanization, it can affectively change the mask complexity while maintains the shape of mask. The result of
segmentation length impact on writing time and lithography performance at full-chip is presented. MRC is another
important factor in mask manufacturability which needs to be carefully studied. Mask pattern transfer fidelity and
inspectability at various selected MRC rules are also presented in the paper.
Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.
Many issues need to be resolved for a production-worthy model based assist feature
insertion flow for single and double exposure patterning process to extend low k1 process
at 193 nm immersion technology. Model based assist feature insertion is not trivial to
implement either for single and double exposure patterning compared to rule based
methods. As shown in Fig. 1, pixel based mask inversion technology in itself has
difficulties in mask writing and inspection although it presents as one of key technology to
extend single exposure for contact layer. Thus far, inversion technology is tried as a cooptimization
of target mask to simultaneously generate optimized main and sub-resolution
assists features for a desired process window. Alternatively, its technology can also be
used to optimize for a target feature after an assist feature types are inserted in order to
simplify the mask complexity. Simplification of inversion mask is one of major issue
with applying inversion technology to device development even if a smaller mask feature
can be fabricated since the mask writing time is also a major factor. As shown in Figure 2,
mask writing time may be a limiting factor in determining whether or not an inversion
solution is viable. It can be reasoned that increased number of shot counts relates to
increase in margin for inversion methodology. On the other hand, there is a limit on how
complex a mask can be in order to be production worthy. There is also source and mask
co-optimization which influences the final mask patterns and assist feature sizes and
positions for a given target. In this study, we will discuss assist feature insertion methods
for sub 40-nm technology.
Due to shrinking design nodes and to some limitations of scanners, extreme off-axis illumination (OAI) required and
its use and implementation of assist features (AF) to solve depth of focus (DOF) problems for isolated features and
specific pitch regions is essential. But unfortunately, the strong periodic character of OAI illumination makes AF's print
more easily. Present OPC flows generate AFs before OPC, which is also causes some AF printing problems. At present,
mask manufacturers must downsize AF's below 30nm to solve this problem. This is challenging and increases mask cost.
We report on an AF-fixer tool which is able to check AF printability and correct weak points with minimal cost in
terms of DOF after OPC. We have devised an effective algorithm that removes printing AF's. It can not only search for
the best non-printing AF condition to meet the DOF spec, but also reports uncorrectable spots, which could be marked as
design errors. To limit correction times and to maximize DOF in full-chip correction, a process window (PW) model and
incremental OPC method are applied. This AF fixer, which suggests optimum AF in only weak point region, solves AF
printing problems economically and accurately.
Optical proximity correction (OPC) of contact-hole printing is challenging since its two dimensional shapes requires
through understanding of lithographic processes compared to one dimensional line and space pattering. Moreover,
recently, it is common to use "elongated contact holes" with large contact area, rather than simple circular ones, for small
electrical resistance. These elongated contact holes make it even more difficult to generate a good OPC model than the
circular ones because the elongated contact-hole patterning causes the asymmetric process effects. For example, impacts
of mask CD error, resist diffusion and resist development are different depending on the orientation of the elongated
contact holes. This paper presents how the OPC model for the elongated contact-hole can be improved as the mask CD
error compensation, accurate resist diffusion model and a new Variable Threshold Model (VTM) are applied for the
asymmetric process effects.
During early stage of a memory device development, photolithography engineer provide
a lithography friendly layout to a designer and assist in development of design rule.
Most of the cases, lithographer relies on the accuracy of lithography simulator to
generate some guidelines and/or modifications to a designer which may be sufficient for
a cell only design. Even for such a cell only designs, it is increasingly difficult to
perform such task due to shrinkage of chip design. For some random pattern design
contained in a core and periphery regions, a more rapid method of evaluating the layout
is needed. In order to perform a fast evaluation, a calibrated proximity model is
needed. If a calibration data is available, a layout can be OPCed and verified to detect
weak spots. On the other hand, a calibration data may not be available during early
design stage. In this paper, a method of obtaining lithography model without the need
of calibration data is presented. First, an illumination source optimization is
performed on the specific patterns to minimize the effect of critical dimension variation.
Using the illumination condition obtained, an optical model is used to determine the
first level layout weak spots which are most critical to a specific layer type based on the
image quality analysis. At this point, one may choose to perform OPC using the
optical model and analyze the process margin. A further interest is on whether if a
particular model can by-pass the need for OPC layout in verifying the layout.
Many issues need to be overcome in creating a production-worthy sub-k1 (<0.25) process. The
repeating photo-etch sequential method for clear and dark mask type is susceptible to overlay
issues while accuracy of first pattern is critical for the space technology. Both technologies
require improved model accuracy and process margin. Because of this, even traditionally noncritical
regions of a layout may contain process margin-limiting defects for double patterning
technology. An integrated OPC-Verification-Selective OPC procedure is developed to improve
quality of results for non-critical regions while retaining fast TAT. The first step utilizes a fast
OPC method with reduced TAT. Next, a lithographic verification tool is used to perform a
thorough check of the OPC results, including process window analysis. This determines which
points limit process margin. Finally, advanced OPC methods are applied to reprocess the areas
limiting process margin. These advanced OPC techniques may include broader lithographic
analysis, field-based correction and process window consideration. Since advanced OPC
methods are only applied to part of the design, TAT is fast. TAT can be further improved by
treating critical regions differently. Critical regions will not be processed in the initial OPC or
intermediate verification steps, but will be corrected by the advanced OPC methods. This
methodology is called Incremental OPC as it applies the most appropriate OPC techniques to
each area of the design. As a result, process margin limiting defects, side-lobe printing and subresolution
assist feature printing can be eliminated prior to mask tape-out with minimal impact
to TAT. In this paper, Incremental OPC is compared to "all-or-nothing" OPC techniques which
must be applied across an entire pattern.
It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard
OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely
long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light
implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and
presents how to solve the problems.
Several criteria are applied to optimize the best illumination and bias condition for a layer. Normalized image log-slope
(NILS) and mask error enhancement factor (MEEF) are promising candidates to simply decide the optimized condition.
NILS represents imaging capability and MEEF represents the mask uniformity influence on wafer image. MEEF has
inversely relationship with NILS, but the optimized point of NILS does not exactly coincide with that of MEEF. Besides
NILS and MEEF, the depth of focus (DoF) is an important factor for defining the process margin. The process window
(PW) is expressed by DoF and exposure Latitude (EL). PW is general parameter used to determine the best lithographic
condition. Large EL can be obtained at the condition with good image performance. In order to include mask uniformity
effect in PW analysis, the common PW overlapping the final layout with positive and negative biased layouts is adopted.
Starting with the minimum NA, sigma and threshold, OPC is performed to satisfy the target layout using aerial image
model, and the final OPCed layout is obtained. The positive and negative biased layouts are generated from the final
OPCed layout. The bias limit is determined considering mask uniformity. The common PW obtained by overlapping the
final layout with positive and negative biased layouts is calculated. Then, NA, sigma and threshold are increased until
the maximum values are reached. The common PW at each NA, sigma and threshold value is obtained using the same
flow sequence. Comparing among calculated PWs, the NA, sigma and threshold of the maximum PW can be chosen as
the best illuminator and bias condition. In this paper, the optimized illumination and bias condition is determined using
PW for 60 nm memory device. The process flow is implemented by an OPC tool. By using the OPC tool for the
illuminator optimization, the actual layout and multiple monitoring points can be measured. In spite of a large number of
calculations, the fast calculation speed can be obtained by using the distributed process.
Traditional approach to model based optical proximity correction method is to collect a set of 1-D and
2-D test pattern data, calibrate a scalar or vector model at constant or variable threshold and modify the
physical layout to obtain the desired layout. Optical proximity corrected layout is obtained by minimizing
the error between the target and the printed image iteratively using a calibrated single model to generate a
simulated print image of mask pattern of variety of field polarity. A similar approach can be extended to
incorporate the final silicon image using a lumped model or tandem photo-resist development and etch
process models. Recently, some have begun to incorporate differing models at specific regions of the
The basic underlying assumption of a model-based OPC requires one to generate a simulated contour
that provides close approximation of wafer image using a calibrated model. During iterative OPC
procedure, not all of the regions of OPC polygons are simulated. That is, sparse sampling of each polygon
is performed to reduce the number of error calculations required and such calculation points are referred to
as an evaluation site. A careful selection of sampling site must be performed to capture optical proximity
effect and obtain the desired OPC. In this paper, utilization of multiples models to generate contour to
accurately define the 2D pattern locally, and implementation of its models throughout the layout is
presented in order to improve accuracy of variety of contact pattern types present in a layout. Hence, the
basic concept is to apply differing models at localized region and achieve greater OPC accuracy than a
single calibrated model.
In particular, a target layout may contain a contact and bar-type structures for the purpose of device
fabrication process step simplifications. Essentially, two different pattern types need to be OPCed, and in
order to perform model based OPC on such a layout, a model for each contact type is generated separately
using a best-fit adaptive search method of optical illumination conditions, aerial image diffusion parameter
and double Gaussian mask loading terms as a main regression parameters. As it terms out, it is difficult to
generate a single model that calibrates to both the contact and bar-type structures and a distinct shift in
empirically calibrated threshold levels exists, and a preferred method is to generate models suited for
contact and bar-type structures separately in order to improve the model and OPC accuracy. However,
each model type needs to be applied at specific locations of a pattern, and a proper OPC recipe for handling
biasing of each pattern type is needed as well as correction scheme suitable for each pattern type is required.
In this paper, we describe an OPC methodology for merged direct contact layout using a proposed pattern
specific modeling and correction technique, and the experimental results indicate that this methodology provides ADI 3s target skew value of 14 nm and ACI 3σ target skew value of 17 nm on a 60 nm half pitch
Virtual OPC concept is suggested for soothing the problem that the roadmap of semiconductor devices proceeds the rate of development of exposure tools. Virtual OPC uses the simulated CD data for an OPC modeling instead of the measured CD data. For successful virtual OPC, the extreme accuracy of the simulation is required for obtaining the simulated CD data close to the actual CD values. In this paper, our efforts to enhance the simulation accuracy are presented and the accuracy of simulated sample data for OPC is verified. The applicability of virtual OPC to the production of devices was verified by performing the virtual OPC using the simulated sample data at 1.2 NA lithography and the result also is presented.
A new framework has been developed to model 3D thick mask effects for full-chip OPC and verifications. In addition to
electromagnetic (EM) scattering effects, the new model also takes into account the non-Hopkins oblique incidence
effects commonly found in real lithography systems but missing in prior arts. Evaluations against rigorous simulations
and experimental data showed the new model provides improved accuracy, compared to both the thin-mask model and
the thick-mask model based on Hopkins treatment of oblique incidence.
Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask
topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model
error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such
as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is
also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a
good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the
phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.
In order to perform an optical proximity correction of memory device nodes below half-pitch 50nm, so called 3D mask
effects need to be included in a model based OPC. As the mask pitch approaches wavelength of an optical system, and
the angle of off-axis illumination becomes increasingly greater than normal incident beam, combined effects of
transmission loss and mask induced polarization induces deviations from Kirchhoff thin mask approximation. Presently,
just a handful of methods are being developed for commercial use in full-chip scale optical proximity correction: edge
domain decomposition method (DDM), rim-type boundary layer and more recently, M3D model [1-6]. However, these
methods currently require extensive modeling and proximity correction runtime although its methods are being
continously improved for accuracy and speed. In this work, some results on an alternative approach to 3D mask
modeling that is suitable for OPC are presented. Using modeling test pattern experimental data and FDTD rigorous
simulation results, a thin mask approximation and alternative 3D mask approximate approaches are compared. And the
results indicate improved model accuracy in terms of root mean square of 30% for a cross-pole and a dipole illumination
conditions, respectively, while the OPC run-time remained similar. Furthermore, a flash memory gate-poly OPC results
using the 3D mask approximate model indicates improved correlation to experimental results than a thin mask model at
minimum resolution dense feature and narrow space regions.
Thin mask and proposed approximate 3D mask models were calibrated for three differing illumination conditions: two
X-dipole illuminations with Y-linear polarization and cross-pole quasar illumination with X&Y-linear polarization
states. For each of the extreme off-axis illumination conditions, 3D mask approximate model developed for OPC
indicated improved calibration results to both test pattern wafer images and rigorous simulation results. In addition,
OPC layout image contours of 3D mask approximate model correlated better to wafer image than the thin mask
approximation at nominal and defocus conditions.
We present simplified symmetric boundary layer model (BLM) for Optical Proximity Correction (OPC) in order to account for thick (or 3D or topographic) mask effect. In this approach, near-field mask image which is quite different from original mask pattern due to mask topography is approximated as the original pattern and boundary layer around it. In this work, the boundary layer is determined as such that residual critical dimension (CD) error between measured CD and modeled CD from the BLM is minimized for various types of features. In case of sub-50 nm memory patterning, this BLM shows sufficient accuracy that root mean square of the residual CD is as small as 4.3 nm. Also, OPC speed with BLM is reasonably fast as the OPC time with BLM increases as only around twice as the conventional OPC time without BLM, which is acceptable in practice.
Rapidly decreasing critical dimension is demanding new RET technologies like PSMgate, customized strong off-axis, and Double Exposure. Among them, Double Exposure is becoming a stronger candidate as throughput issue is getting better because of exposure tool's enhancement. Indeed, immersion is not fully ready and many semiconductor manufacturing companies want to extend their exposure tools for sub 55nm process. So, Double Exposure has been studied for a long time and suggested by many lithographers for sub 55nm process. For Logic device, it has many challenges to make Double Exposure work like need for model based layer decomposition. But for Memory device such as DRAM and FLASH, there is a good way to make Double Exposure flow robust because its design is not that random like Logic Device. In this paper, we will investigate and show how to implement robotic Double Exposure using two typical Double Exposure illumination combinations, Dipole-Ann and Double Dipole.
Design for Manufacturing (DFM) is being widely accepted as one of keywords in cutting edge lithography and OPC technologies. Although DFM seems to stem from designer's intensions to consider manufacturability and ultimately improve the yield, it must be well understood first by lithographers who have the responsibility of reliable printing for a given design on a wafer. Current lithographer's understanding of DFM can be thought of as a process worthy design, and the requirements set forth from this understanding needs to be well defined to a designer and fed forward as a necessary condition for a robust design. Provided that these rules are followed, a robust and process worthy design can be achieved as a result of such win-win feed-forward strategy. In this paper, we discuss a method on how to fully analyze a given design and determine whether it is process worthy, in other words DFM-worthy or not. Mask Error Enhancement Factor (MEEF), Through Focus MEEF (TF-MEEF) and Mean-To-Target (MTT) values for an initial tentative design provide good metrics to obtain a robust and process worthy design. Two remedies can be chosen as DFM solutions according to the aforementioned analysis results: modify the original design or manipulate the layout within a design tolerance during OPC. We will discuss on how to visualize the analyzed results for the robust and process worthy OPC with some relevant examples. In our discussions, however, we assumed that the robust model be being used for each design verification, and such a model derived with more physical parameters that correlates better to real exposure behavior. The DFM can be viewed as flattening the TF-MEEF across the design.
In this work, a potential drawback of simultaneously representing a set of data that contains line-ends, isobar, block structure, and pitch linearity intensity signal using a single representative model have been resolved. In a typical model-OPC procedure, a set of pattern data representative of OPC layout is calibrated using a single representative model, and this model may be a scalar or a vector at constant threshold or variable threshold. Nevertheless, traditional methodology treats a set of pattern data as a whole believing that it provides a best representation of a more complicated environment. In this study, pattern type specific models are used to perform optical proximity correction. This multi-model approach distinguishes each pattern type and specified pitch range a priori to obtaining intensity signal by checking for neighboring segment. Based on this search result, its segment is classified into a pattern type and sub-group, and then, pattern specific models are applied. This approach provides improved calibration result for strong off-axis illumination and optical proximity correction result which will be difficult to achieve with a single representative model.
While optical lithography is being pushed to its limits, there is a general concern as to which metrology tool is more suitable for inspection of new generation devices. Scatterometry is one of the few types of metrology that has true in-situ potential for deep submicron critical dimension and profile analysis. Physical metrology is the key element in maintaining adequate and affordable process latitude in lithography processing. Accurate metrology is needed for characterizing and monitoring the processing states, such as exposure, focus, post-exposure bake (PEB), critical dimension (CD) resolution, and uniformity. In addition, scatterometry is a good candidate tool to obtain data necessary to perform model-based optical proximity correction (OPC). However, it is unknown as to current scatterometry provides necessary sensitivity to yield results acceptable for OPC usage. In this paper, we have utilized scatterometry to measure test patterns used in a model-based OPC and performed OPC on DRAM bitline core and periphery adjoining region then, its results are compared to those model-based OPC performed using data obtained from CD-SEM and V-SEM. In doing so, we have attempted to obtain an ideal model which provides best performance in context of OPC. Furthermore, we have discussed 1-D and 2-D types of test patterns that are acceptable for OPC purpose and provided the verification results for each model using commercially available software.