As the scales of the semiconductor devices continue to shrink, accurate measurement and control of the overlay have been emphasized for securing more overlay margin. Conventional overlay analysis methods are based on the optical measurement of the overlay mark. However, the overlay data obtained from these optical methods cannot represent the exact misregistration between two layers at the circuit level. The overlay mismatch may arise from the size or pitch difference between the overlay mark and the real pattern. Pattern distortion, caused by CMP or etching, could be a source of the overlay mismatch as well. Another issue is the overlay variation in the real circuit pattern which varies depending on its location. The optical overlay measurement methods, such as IBO and DBO that use overlay mark on the scribeline, are not capable of defining the exact overlay values of the real circuit. Therefore, the overlay values of the real circuit need to be extracted to integrate the semiconductor device properly. The circuit level overlay measurement using CDSEM is time-consuming in extracting enough data to indicate overall trend of the chip. However DBM tool is able to derive sufficient data to display overlay tendency of the real circuit region with high repeatability. An E-beam based DBM(Design Based Metrology) tool can be an alternative overlay measurement method.<p> </p> In this paper, we are going to certify that the overlay values extracted from optical measurement cannot represent the circuit level overlay values. We will also demonstrate the possibility to correct misregistration between two layers using the overlay data obtained from the DBM system.
As design rule shrink, overlay has been critical factor for semiconductor manufacturing. However, the overlay
error which is determined by a conventional measurement with an overlay mark based on IBO and DBO often
does not represent the physical placement error in the cell area. The mismatch may arise from the size or pitch
difference between the overlay mark and the cell pattern. Pattern distortion caused by etching or CMP also can
be a source of the mismatch. In 2014, we have demonstrated that method of overlay measurement in the cell
area by using DBM (Design Based Metrology) tool has more accurate overlay value than conventional method
by using an overlay mark. We have verified the reproducibility by measuring repeatable patterns in the cell area,
and also demonstrated the reliability by comparing with CD-SEM data.
We have focused overlay mismatching between overlay mark and cell area until now, further more we have
concerned with the cell area having different pattern density and etch loading. There appears a phenomenon
which has different overlay values on the cells with diverse patterning environment. In this paper, the overlay
error was investigated from cell edge to center. For this experiment, we have verified several critical layers in
DRAM by using improved(Better resolution and speed) DBM tool, NGR3520.
Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.
Extreme ultraviolet lithography (EUVL) is one of the most leading lithography technologies for high volume manufacturing. The EUVL is based on reflective optic system therefore critical patterning issues are arisen from the surface of photomask. Defects below and inside of the multilayer or absorber of EUV photomask is one of the most critical issues to implement EUV lithography in mass production. It is very important to pick out and repair printable mask defects. Unfortunately, however, infrastructure for securing the defect free photomask such as inspection tool is still under development furthermore it does not seem to be ready soon. In order to overcome the lack of infrastructures for EUV mask inspection, we will discuss an alternative methodology which is based on wafer inspection results using DBM (Design Based Metrology) tool. It is very challenging for metrology to quantify real mask defect from wafer inspection result since various sources are possible contributor. One of them is random defect comes from poor CD uniformity. It is probable that those random defects are majority of a defect list including real mask defects. It is obvious that CD uniformity should be considered to pick out only a real mask defect. In this paper, the methodology to determine real mask defect from the wafer inspection results will be discussed. Experiments are carried out on contact layer and on metal layer using mask defect inspection tool, Teron(KLA6xx) and DBM (Design Based Metrology) tool, NGR2170™.