As we presented in the last conference, it is much difficult to get down the k1 limit of EUV lithography compared to that of optical lithography especially recent immersion lithography. Even though current 0.33NA NXE3300 tool has enhanced aberration characteristics and variable illumination mode than its predecessor, ADT and NXE3100, still there are limitations related with resolution capability of EUV lithography. First of all, photon shot noise and immature resist performances play an important role in patterning of very fine patterns. As already known, low sensitivity resists have been widely used to reduce shot noise. However, when considering productivity in EUV lithography, high sensitivity resists are inevitable, so it is necessary to increase image contrast by reducing scanner blur like aberration, M3D, stray light et al. We have investigated the impact of aberration and limitation in illumination pupil fill ratio in EUV. In particular, the aberration sensitivity is different by the illumination conditions, this was intensified when using the particular pupil. Because the lens calibration is conducted with standard illumination condition in NXE3300, it is necessary to consider different aberration sensitivity in accordance with pattern and used pupil condition in EUV lithography. To ensure the process margin of tech node close to limit, a flexpupil with low pupil fill ratio (PFR) than 0.2 were required. Hence in order to avoid through-put loss at this condition, the new concept of the illuminator design is required without light loss. Contamination of collector mirror can affect the patterning also. We will also report about the patterning effect of pupil deformation by degraded collector in low PFR condition.
Sub 0.3k1 regime has been widely adopted for high volume manufacturing (HVM) of optical lithography due to various resolution enhancement technologies (RETs). It is not certain when such low k1 is feasible in EUV, though most technologies are available in EUV also. In this paper, experimental results on patterning performance of line space (L/S) and contact hole (C/H) in EUV lithography will be presented. First, practical k1 value with 0.33NA EUV lithography was investigated through experiment using NXE3300 EUV tool. Patterning limit, as defined by local critical dimension uniformity (LCDU) for C/H array pattern were measured with respect to various design rules. It was evaluated that the effect of off axis illumination (OAI) mode with various illumination conditions to improve the patterning performance and to reduce k1 limit. Then the experimental results of LCDU were compared with normalized image log slope (NILS) values from simulation. EUV source mask optimization (SMO) technologies to increase NILS with FlexPupil option of EUV scanner were evaluated and possibility of further improvement was also discussed.
Extreme Ultraviolet (EUV) is the most promising technology as substitute for multiple patterning based on ArF immersion lithography. If enough productivity can be accomplished, EUV will take main role in the chip manufacturing. Since the introduction of NXE3300, many significant results have been achieved in source power and availability, but lots of improvements are still required in various aspects for the implementation of EUV lithography on high volume manufacturing. Among them, it is especially important to attain high sensitivity resist without degrading other resolution performance. In this paper, performances of various resists were evaluated with real device patterns on NXE3300 scanner and technical progress of up-to-date EUV resists will be shown by comparing with the performance of their predecessors. Finally the prospect of overcoming the triangular trade-off between sensitivity, resolution, line edge roughness (LER) and achieving high volume manufacturing will be discussed.
As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.
Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.
ASML NXE3100 has been introduced for EUV Pre-Production, and ASML NXE3300 for High Volume Manufacturing will be installed from this year. EUV mask defect control is the one of the concerns for introducing EUVL to device manufacturing, for current EUV mask defect level is too high to accept for device volume production. EUV mask defects
come from mask blank, mask process and mask handling. To have reduced mask defect level, quality control of blank
mask, optimization of EUV mask process and improvement of EUV mask handling need to be ready. In this paper, we analyze printed defects exposed from EUV full field mask at NXE3100. For this analysis we trace mask defects from mask to wafer printing. From this we will show current EUV mask’s defect type and numbers. Acceptable defect type, size and numbers for device manufacturing with EUVL will be shown. Through investigating printing result of natural ML defects, realistic level of natural ML defects will be shown.
In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most
powerful candidate for patterning. So It has being studied to overcome the several issues such as source
power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution,
LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on.
For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so
far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography
and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for
3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately,
EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit
high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result.
Therefore it needs a lot of efforts to improve and compete against double patterning.
The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we
will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several
methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with
that of double patterning in terms of CD uniformity and pattern profile.
Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV
causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field
CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection
from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD
measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts
from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the
experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be
not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black
border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA
Extreme Ultra-Violet (EUV) lithography is almost only solution reachable for next-generation lithography below 30nm
half pitch with relative cost competitiveness. In this study, we investigate the feasibility of EUV lithography for applying
2X nm dynamic random access memory (DRAM) patterning. Very short wavelength of 13.5nm adds much more
complexity to the lithography process. To understand for challenges of EUV lithography for high volume manufacturing
(HVM), we study some EUV specific issues by using EUV full-field scanners, alpha demo tool (ADT) at IMEC and pre-production
tool (PPT) at ASML. Good pattern fidelity of 2X nm node DRAM has been achieved by EUV ADT, such as
dense line and dense contact-hole. In this paper, we report on EUV PPT performance such as resolution limit, MEEF,
across slit CD uniformity (CDU) and focus & exposure latitude margin with 2X nm node DRAM layers in comparison
with ADT performance. Due to less flare and aberration of PPT, we have expected that PPT shows good performance.
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. EUV Pre-Production Tool
(PPT) is expected to be available at the end of 2010. As EUVL era comes closer, EUVL infrastructure has to get mature
including EUVL mask stack. To reduce HV CD bias which comes from shadowing effect, thin mask stack has been
considered. We presented that EUVL mask with 58nm absorber height shows same printing performance with
conventional EUVL mask with 80nm absorber height in our previous work. CD change and pattern damage at the
exposure field edges due to light leakage from the neighboring fields were also demonstrated.
In this paper, optimal mask stack which shows lower H-V CD bias than conventional structure using 70-nm-thick
absorber is proposed. To find minimized absorber height for sub-32nm pattering experimentally, printing result of
conventional mask and thin mask stack with 1:1 L/S patterns will be compared. Further-on, we demonstrate the printing
result of the reticle which is designed to minimize CD error at the exposure field edges due to mask black border
reflectivity by reducing reflectivity from the absorber.
All the wafers are exposed at ASML Alpha Demo Tool (ADT) and Pre-Production Tool (PPT) S-litho EUV is used for
Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout
correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in
EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated
PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real
device is measured experimentally with real device layout with clearing pads in it.
Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount
of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.
Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm
line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns
by simulation. However various reports have been presented on mask shadowing bias correction, experimental results
are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are
taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer
EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which
allows us less shadowing effect with minimum loss of process window.
In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and
process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the
printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V
CD bias and process window will be presented.
In this paper, we will present applications of MoSi-based binary intensity mask for sub-40nm DRAM with hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination and mask materials in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of
binary intensity mask are used for this experiment; those are ArF att.PSM ( MoSi:760Å , transmittance 6% ),
conventional Cr ( 1030Å ) BIM (Binary Intensity Mask), MoSi-based BIM ( MoSi:590Å , transmittance 0.1%) and multi
layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA immersion scanner are performed to study
influence of mask structure, process margin and effect of polarization. Two types of DRAM cell patterns are studied; one
is a line and space pattern and the other is a contact hole pattern through mask structure. Various line and space pattern is
also through 38nm to 50nm half pitch studied for this experiment. Lithography simulation is done by in-house tool based
on diffused aerial image model. EM-SUITE is also used in order to study the influence of mask structure and
polarization effect through rigorous EMF simulation. Transmission and polarization effects of zero and the first
diffraction orders are simulated for both att.PSM and BIM. First and zero diffraction order polarization are shown to be
influenced by the structure of masking film. As pattern size on mask decreases to the level of exposure wavelength,
incident light will interact with mask pattern, thereby transmittance changes for mask structure. Optimum mask bias is
one of the important factors for lithographic performance. In the case of att.PSM, negative bias shows higher image
contrast than positive one, but in the case of binary intensity mask, positive bias shows better performance than negative
one. This is caused by balance of amplitude between first diffraction order and zero diffraction order light.1
Process windows and mask error enhancement factors are measured with respect to several types of mask structure. In
the case of one dimensional line and space pattern, MoSi-based BIM and conventional Cr BIM show the best
performance through various pitches. But in the case of hole DRAM cell pattern, it is difficult to find out the advantage
of BIM except of exposure energy difference. Finally, it was observed that MoSi-based binary intensity mask for sub-
40nm DRAM has advantage for one dimensional line and space pattern.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask
are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask),
thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA
immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two
types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node
pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this
experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also
used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation.
Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First
and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on
mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance
changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case
of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive
bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order
and zero diffraction order light.
Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1
levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance
through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of
BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary
intensity mask for sub-45nm has advantage for one dimensional line and space pattern.
Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process
issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern.
Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two
types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the
implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and
the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also
considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone,
and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm
DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.
Scanning Electron Microscope (SEM) has been typical methods for measuring CD of nanopatterns until ArF process was introduced. However in case of ArF process, this method has serious drawback such as shrinkage of organic material by the irradiation of high-energy electron beam. The optical scatterometry system is considered to be promising method for measuring CD due to no damage on organic materials. Sub-80nm node gate was selected because of its measurement stability. CD, profile and thickness are compared with those measured by CD-SEM, cress-section SEM. The correlation degree is shown as GOF, R2, and Profile. Based on merit of speed, easiness and accurate measurement, optical CD method has been applied to CD uniformity. CD uniformity measured by OCD was very similar to that measured by SEM on gate pattern. Based on this result, OCD was applied for the improvement of CD uniformity combined with ASML's does-mapper in technology. We investigated the variation of thickness of organic BARC over topology of various size line and space patterned poly-Si by OCD.