An optical logic system is being developed to test the packaging and operation of free space optical logic systems. It uses symmetric-self-electro-optic effect devices as the logic elements and vertical cavity surface emitting lasers (VCSELs) to provide the optical inputs. This paper discusses the issues involved with incorporating the VCSEL array into the system. Issues that are investigated include beam combining, electrical drive, and VCSEL polarization. We find that current experimental devices are appropriate for early system experiments although issues such a multimode operation and the resulting current dependent polarization need to be addressed for practical systems.
A cellular logic image processor was designed, constructed and successfully operated by interconnecting two arrays of symmetric self electro-optic effect devices (S-SEED). This paper outlines some of the design issues associated with the implementation of a free-space digital optical system.
Proc. SPIE. 1505, Optics for Computers: Architectures and Technologies
KEYWORDS: Beam splitters, Logic, Digital image processing, Detection and tracking algorithms, Image processing, Computing systems, Control systems, Signal processing, Computer architecture, Binary data
The construction of digital optical processors based on the cellular logic image processor (CLIP) architecture is discussed. Both a single-channel processor and a parallel version incorporating 256 information channels have been constructed. The single channel version of the processor allows eight different combinatorial logic processes to be carried out under electronic control and can be programmed in real time. Several algorithms including pattern recognition, byte comparison, full addition and subtraction have been implemented with this machine. The 256 channel version operates similarly to the single channel version except that a reduced instruction set internal processor with four selectable logic processes is used. A nearest neighbor interconnect provides the communication required between the different information channels. More advanced processing capability can be achieved with the introduction of such non-local interconnects as shuffle networks. Results and simulations obtained with these processors are presented. Advances in the various components of the O- CLIP circuit, future goals, and potential application are also discussed.