Maskless lithography based on electron beam parallelization requires well adapted data links, capable of transmitting the corresponding data volume at rates up to the Tbps domain. In this paper we focus on two key components, the high-speed data buffer unit and the integrated optical receiver, which are part of a scalable (24 - 140 Gbps) optical data link. The high-speed buffer design architecture enables the transmission of skew-compensated parallel data in the range of 50 Gbps. The 45-channel low-noise integrated optical receiver chip based on BiCMOS 0.6 micron technology is capable of an overall transmission capacity of 140 Gbps.
Maskless lithography based on electron beam parallelization requires well adapted data links, capable of transmitting the corresponding data volume at rates up to the Tbps domain. In this paper we focus on a scalable (24 - 140 Gbps) optical data link, well adapted for future implementation in maskless lithography systems. The link comprises a high-speed data buffer with synchronizable architecture and scalable throughput (N x 24 Gbps), an optical free space transmission solution, a 45 channel low-noise optical receiver chip based on BiCMOS 0.6 micron technology and, finally, a Data Processor & Demux IP core implemented in VHDL.
Maskless lithography is one of the possible solutions to manage the escalating mask costs and demands for faster production cycles. One of the major issues with the maskless lithography technology however is the management and transfer of the enormous data volumes required to define the chip structures. Ensuring competitive and reliable operation requires dedicated preparation and buffering of the lithography data to be transmitted to the exposure unit. An optimized dedicated architecture and careful signal integrity design for proper functionality are needed due to the high data rates and the highly parallelized system operation. This paper presents the implementation aspects and the design of a high-speed transmission system solution for maskless lithography systems. The introduced solution treats a field programmable gate array (FPGA) based implementation for a latency-sensitive high speed lithography system.