Design rules (DRs) are the primary abstraction between design and manufacturing. The optimization of DRs to achieve
the correct tradeoff between scaling and yield is a key step in developing a new technology node. In this work we propose
a design-of-experiments based framework to optimize DRs, where layouts are generated for different DR values using
compaction. By analyzing the impact of DRs on layout scaling, we propose a novel Boolean minimization based approach
to reduce the number of layouts that need to be generated through compaction. This methodology provides an automated
approach to analyze several DRs simultaneously and discover area-critical DRs and DR interactions. We apply this
methodology to middle-of-line (MOL) and Metal1 layer design rules for a commercial 20nm process. Our methodology
results in 10 - 105 x reduction in the number of layouts that need to be generated through compaction, and demonstrates
the impact of MOL and Metal1 DRs on the area of some standard cell layouts.
Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in
the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate
design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation
is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization.
In this work, we develop a predictive model of device linewidths after optical proximity correction (OPC) across the process
window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip
scale without actually performing OPC and litho simulation.
To model litho effects on 2D poly geometries in standard cell layouts, we rigorously identify layout parameters that
affect the litho contour. We classify gate poly (devices) into different categories based on their geometric parameters as
well as those of neighboring field poly shapes. To create a model, we create a design of experiments (DOE) for all device
categories and perform OPC followed by through-process window litho simulation. To limit the runtime of OPC and
litho simulation for the DOE, we reduce the layout parameter space with a rigorously qualified methodology for filtering
out unimportant parameters. To allow prediction of the device contour, we model the device edge placement error (EPE)
using a response surface methodology followed by polynomial regression. We have implemented our predictive linewidth
modeling with foundry 90nm and 65nm technology, along with industry-strength OPC models and recipes. Using the
regression models, we have performed prediction on standard-cell blocks and achieved a 3σ prediction accuracy of 2nm
across the process window.
In this work we present a predictive model for the edge placement error (EPE) distribution of devices in standard library cells based on lithography simulations of selective test patterns. Poly-silicon linewidth variation in the sub-100nm technology nodes is a major source of transistor performance variation (e.g., Ion and Ioff) and circuit parametric yield. It has been reported that significant part of the observed variation is systematically impacted by the neighboring layout pattern within optical proximity. Design optimization should account for this variation in order to maximize the performance and manufacturability of chip designs. We focus our analysis on standard library cells. In the past the EPE characterization was done on simple line array structures. However, the real circuit contexts are much more complex. Standard library cells offer a nice balance of usability by the designers and modeling complexity. We first construct a set of canonical test structures to perform lithography simulations using various OPC parameters and under various focus and exposure conditions. We then analyze the simulated printed image and capture the layout-dependent characteristics of the EPE distribution. Subsequently, our model estimates the EPE distribution of library cells based on their layout. In contrast to a straight-forward simulation of the library cells themselves, this approach is computationally less expensive. In addition the model can be used to predict the EPE distribution of any library cells and not limited to those that are simulated. Also, since the model encapsulates the details of lithography, it is easier for designers to integrate into design flow.
Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of design-aware OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.
In high-voltage electron beam lithography, most of the beam energy is released as heat and accumulates in the local area of writing. Excessive heat causes changes in resist sensitivity, which in turn causes significant critical dimension (CD) variation. Previous methods for reducing CD distortion caused by resist heating include usage of lower beam currents, increased delays between electron flashes, and multi-pass writing. However, all these methods lower mask writing throughput. This leads to increased mask writing cost, which is increasingly becoming a major limiting factor to semiconductor industry productivity. In this paper, we propose a new method for minimizing CD distortion caused by resist heating. Our method performs simultaneous optimization of beam current density and subfield writing order. Simulation experiments show that, compared to previous methods, the new subfield scheduling method leads to significant reductions in resist temperature with unchanged mask writing throughput. Alternatively, subfield scheduling can be coupled with the use of higher beam current densities, leading to increased writing throughput without increasing CD distortion.
Resist heating is one of the largest contributors to critical dimension (CD) distortion in electron beam photomask fabrication. Previous methods for reducing CD variation caused by resist heating include lower beam currents, increased delays between electron flashes, and writing in multiple passes. However, all these methods lower mask writing throughput. This leads to increased mask writing cost, which is increasingly becoming a major limiting factor to semiconductor industry productivity. In this work, we investigate a new degree of freedom for mitigating CD distortion caused by resist heating. By optimizing the sequence in which subfields are being written, it is possible to reduce CD variability caused by resist heating, without significantly increasing the mask writing time.