Novel through-die front-to-back connections for MEMS applications are described. Large diameter (~100 μm diameter) front-to-back through-die connections have been studied previously for MEMS applications. Multi-level through-die hole structures are proposed here to overcome problems of large diameter through-die holes (lesser front-side active area) and facilitate new applications. Two-level versions of such through-die holes comprise of a small front-side hole (<1 μm diameter) and a large back-side hole (~100 μm diameter), or vice versa. Alternatively, multiple small holes from one side can connect to a large hole from the other side. Multiple concentric holes from one surface can be fabricated with appropriate spacer technology. Two-level through-die structures in silicon have been designed, fabrication processes developed, and the resulting structures characterized. New CMP based patterning techniques have been developed for sidewall films on through-die wafers. Two-level through-die holes have been fabricated with 100 μm diameter hole in the back and 5 to 30 μm diameter holes in the front-side with a pitch from 300 μm to 1000 μm. Through-die hole sidewall conductive coatings have been accomplished with CVD Tungsten and in-situ doped LPCVD Polysilicon. Two-level through-die holes have many potential applications, including low impedance ground connections, on-die power/ground distribution, on-die Faraday shielding, on-chip CMOS and MEMS integration, 3D MEMS devices, micro-fluidics, and 3D integration.