Proc. SPIE. 6518, Metrology, Inspection, and Process Control for Microlithography XXI
KEYWORDS: Metrology, Etching, Copper, Atomic force microscopy, Scanning electron microscopy, Transmission electron microscopy, 3D metrology, Process control, Critical dimension metrology, Semiconducting wafers
Accurate, precise, and rapid three-dimensional (3D) characterization of patterning processes in integrated
circuit development and manufacturing is critical for successful volume production. As process tolerances and circuit
geometries shrink with each technology node, the precision, accuracy, and capability requirements for dimension and
profile metrology intensify. The present work adopts the scanning probe based technology, 3D atomic force
microscopy (AFM), to address current and next-generation critical dimension (CD) metrology needs for device features
at a variety of process steps. Fast, direct, and non-destructive 3D profile characterization of patterning processes is a
primary benefit of CD AFM metrology. The CD AFM utilizes a deep trench (DT) mode for narrow and deep trenches,
and a CD mode for linewidth and sidewall profiling. The 3D capability enables one tool for many applications where
conventional scanning electron microscopy (SEM), scatterometry, and stylus profiler tools fall short: Gate etch/resist
linewidth and sidewall cross-section profile, etch depth for high aspect ratio via, STI etch depth, 3D analysis for
MUGFET multi-gate devices, pitch/CD/sidewall angle (SWA) verification for scatterometry targets, and post-CMP
active recess. The AFM is an efficient tool for inline monitoring, rapid process improvement/development, and is a
complementary addition to the dimension metrology family.
Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.
We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.
The 2001 edition of the International Technology Roadmap for Semiconductors establishes line-edge roughness (LER) requirements for patterned resist lines. Little is known, however, about how LER affects device performance or about how much LER is acceptable for a given technology. Our work seeks to answer these questions by combining process modeling, three-dimensional (3D) device modeling, and experiment to investigate the amount of LER that can be varied by process conditions and the levels to which LER must be controlled. Our process models show the expected trade-offs between resist diffusion, LER, and resolution, and they show that much of the high-frequency, high-amplitude roughness can be reduced through appropriate etch and implant diffusion processes. The low-frequency roughness, on the other hand, is much harder to eliminate. Experimentally, we have found that the aerial image quality and the etch process have the largest effect on the edge roughness transferred to polysilicon lines, and the roughness after etch is distributed over a broad range of frequencies. The 3D device models indicate that the amount of roughness that gets transferred to the junctions will dominate the electrical behavior, and the effects will likely be different for PMOS devices than NMOS devices.