The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines and cuts” approach is being used to achieve good pattern fidelity and process margin, with extendibility to ~7nm. In previous work, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 16nm node.[2,3,4,5] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[6,7] This is significant since mask data volumes of <500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In this study, we extend the scaling using SMO with simplified OPC in a technique called “SMOLite” beyond 16nm. The same “cut” pattern is used for each set of simulations, with “x” and “y” locations for the cuts scaled for each node. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops. Another approach for scaling the “cut” pattern has also been studied. This involves the use of a hole pitch division process to create a grid template combined with a relatively large “selection” pattern to create cuts at the desired grid locations. Experimental demonstration of the cut approach using SMO-Lite and a grid template will be presented. Wafer results have been obtained at a line half-pitch of 20nm, which corresponds to the gate pitch at the 10nm node.
An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be
competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1
dimensional GDR layout of 20nm node and below. The simulation under ArF single exposure shows 16nm node of
metal layer and 12nm node of gate layer can be resolved with rectangle mask patterns. For both layers bright field
exposure is used and experimentally positive and negative tone developments are applied for metal layer (island patterns)
and gate layer (cut patterns) respectively. The integrated process through SADP, etching, and so on is shown.
It is found that the simple pattern has lower MEEF than the complicated ones. Applying simple mask pattern MEEF can
be suppressed to be 3~4 even at 16nm node. The SEM images of the masks with simple and complicated shapes show
that it is difficult to reproduce the complicated pattern accurately.
We prepared mask data with various complexities of patterns and evaluated the writing time of an up-to-date EB writer.
The time depends on the shot counts and a typical OPC pattern takes 4 times longer time than rectangle pattern. Since the
cost of writing time is around 20% of the entire cost, the saved cost from OPC pattern to rectangle pattern becomes 15%.
Regarding advanced node of mask with more complicated pattern it takes further longer time and there is an impact on
other technologies of inspection or process. So the saved cost becomes huge.
A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is
shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography
parameters and layout parameters simultaneously is applied that is called co-optimization. At first the memory cell is
optimized from several viewpoints of device and lithography, and then the entire memory cell block including the array
circuit is optimized. It proves that combination of co-optimization and insertion of SRAF works very well considering
the appropriate printed shape required by the device layout. The co-optimization is compared to such a conventional
method as OPC. The performance is better than conventional OPC. Especially the MEFF is much better and the
evaluation to find the mechanism is shown. It proves that complex patterns with many fragments make MEEF higher.
The superior characteristics of co-optimization are analyzed by the result of Linear Programming that can find the strict
solution. The pixel source shape has become almost same as one by co-optimization. The solution is achieved by binary
mask with simple patterns and the simple source shape. It is crucial for COO.
Instead of conventional SMO that iterates illumination source optimization and OPC, new optimization method is
introduced that optimizes illumination source and device layout simultaneously. In this method the layout is described by
a function of layout parameters that defines the layout characteristics and the layout parameters are combined with
source parameters, which forms a composite space of optimization. In this space the source and layout are optimized
simultaneously. This method can search the steepest slope to the solution in the space during optimization, which is
impossible for the conventional SMO. So it can reach the real solution with less probability of being trapped in local
solution. This technology is applied to some cases of lithography targets such as CD and DOF, and good results are
attained with very simple mask. It also works for diagonal patterns that OPC cannot handle easily. In addition more
complicated lithography target such as robustness against MSD of scanner stage vibration is addressed and the
optimization result is useful to resolve problems caused by fluctuation of manufacturing.
Wavefront aberrations of the projection optics induce unignorable focus and overlay errors dependent on the shape of the
device pattern and illumination settings. Thus, the 32nm node and the subsequent double patterning lithographic
generation require ever more stringent control of aberrations. For the most recent exposure tools with polarized
illumination and high throughput capabilities in particular, due attention needs to be paid to the influences of aberrations
caused by polarization and exposure load. A system for measuring and correcting polarization aberrations and lens
heating aberrations has been developed, and its technical details and application examples are presented in this paper.
Furthermore, improvement in aberration control on the next generation exposure tool compatible with double patterning
is stated as well.
In the Hyper-NA immersion age, it is essential to optimize all optical parameters, and so exposure tools must have
functions to precisely control the parameters.
There have been various reports indicating that polarization aberrations of projection optics affect imaging performance,
but there have been few reports on reducing their influence in tools. We have developed a new method to optimize
imaging performance with polarization taken into account.
This paper describes a theoretical analysis of polarization with Pauli decomposition. A strict vectorial calculation of
optical images matches our expression. Then, our solver software can determine the optimum conditions of all
aberration parameters of exposure tools for specific IC patterns.