In this study, a highly conductive and transparent AlN–based glass electrode, fabricated by either DC or AC-pulse-based electrical breakdown processes, is introduced, and applied to AlGaN–based UV-A and UV-C light-emitting diodes with p-AlxGa1-xN contact layers (x = 0.05, 0.1, 0.4). This AlN–based glass electrode with a conducting filament exhibited high transmittance in the deep-UV region (over 95.6 % at 280 nm) and low contact resistance with a p-Al0.4Ga0.6N layer (ρc = 3.2 × 10-2 Ω·cm2). The ohmic conduction mechanism at the interface between the AlN film and p-Al0.4Ga0.6N layers was then examined using various analytical tools. One of the 280-nm top-emitting LEDs with the AlN-based glass electrodes operated stably with a forward voltage of 7.7 V at 20 mA and a light-output power of 7.49 mW at 100 mA after packaging. The external quantum efficiency was measured to be a record-high 2.8. This report is the first demonstration of top emission from DUV LEDs, and the proposed method may be used extensively in various areas of optoelectronic devices and sensors.
OPC models with and without thick mask effect (3D-mask effect) are compared in their prediction capabilities of actual
2D patterns. We give some examples in which thin-mask models fail to compensate the 3D-mask effect. The models
without 3D-mask effect show good model residual error, but fail to predict some critical CD tendencies. Rigorous
simulation predicts the observed CD tendencies, which confirms that the discrepancy really comes from 3D-mask effect.
The k1 factor of the 65nm node device approaches to around 0.3 or even below because the device shrinking is much faster than the development speed of the high NA ArF scanner. Since the conventional model-based OPC (MBOPC) is only focused on patterning of the layout on the wafer as exactly same as the original design, it can hardly guarantee enough process margin in the low-k1 lithography regime. In this paper, illumination shape and retargeting rule of the multi-step OPC are optimized to improve the process margin of the 65nm node memory device. Sigma width and open angle of the dipole illumination is optimized to resolve the minimum pitch and to maintain the critical dimension (CD) uniformity. Even though the illumination is optimized and litho-friendly layout (LFL)  is applied, there is the process weak point caused by the device architecture. Applying the full-chip level verification, it is found that most of process weak points exist in isolated and semi-dense patterns of the core and peripheral region. The full-chip level verification uses the vector thin film model for the accurate resist image simulation of the high NA scanner. As the mask error enhancement factor (MEEF) is getting larger in the 65nm node device, the mask mean to target (MTT) rises as the dominant factor of the process margin. The NILS according to mask MTT variation is adopted as criterion for the process weak point extraction. Since the NILS of process weak point can be improved by the increasing pattern with, retargeting rules such as selective bias and pattern shift are applied. Under the dipole illumination, the NILS distributions of parallel and perpendicular patterns are different and the different retargeting rules are applied to them. Applying proposed illumination and multi-step OPC optimization to the 65nm node memory device, we have validated that our methodology can insure enough process margin for the volume production.