Mid wavelength infrared (MWIR) HgCdTe heterostructures were grown on 3-inch dia Si (211) substrates by the molecular beam epitaxy technique and p+n format devices were fabricated by arsenic ion implantation. Very long wavelength infrared (VLWIR) layers have been employed as interfacial layers to block the propagation of detects from the substrate interface into the HgCdTe epilayers. Excellent material characteristics including the minority carrier lifetime of 7.2 usec at 200K and 2 usec at 80K in the n-HgCdTe absorber layer with 5 um cut-off wavelength at 80K were achieved. The photovoltaic detectors fabricated on these MWIR heterostructures show excellent zero-bias resistance-area product (R0A) on the order of 10<sup>8</sup> ohm-cm<sup>2</sup> and peak dynamic impedances on the order of 109 ohm-cm<sup>2</sup>. A two-step arsenic activation anneal followed by the 'Hg' vacancy filling anneal (third step) is shown to produce the best R0A values, since the intermediate temperature annealing step seems to control the diffusion of arsenic, assisted by the implantation-induced defects. The experimental R0A values are compared with that predicted by theory based on a one-dimensional model, indicating g-r limited performance of these MWIR devices at 80K.
The cost and performance of hybrid HgCdTe infrared focal plane arrays are constrained by the necessity of fabricating the detector arrays on a CdZnTe substrate. These substrates are expensive, fragile, are available only in small rectangular formats, and are not a good thermal expansion match to the silicon readout integrated circuit. We discuss in this paper an infrared sensor technology based on monolithically integrated infrared focal plane arrays that could replace the conventional hybrid focal plane array technology. We have investigated the critical issues related to the growth of HgCdTe on Si read-out integrated circuits and the fabrication of monolithic focal plane arrays: (1) the design of Si read-out integrated circuits and focal plane array layouts, (2) the low temperature cleaning of Si(001) wafers, (3) growth of CdTe and HgCdTe layers on read-out integrated circuits, (4) array fabrication, interconnection between focal plane array and read-out integrated circuit input nodes and demonstration of the photovoltaic operation, and (5) maintenance of the read-out integrated circuit characteristics after substrate cleaning, molecular beam epitaxy growth and device fabrication. Crystallographic, optical and electrical properties of the grown layers are presented. Electrical properties for diodes fabricated on misoriented Si and read-out integrated circuit substrates are discussed. The fabrication of arrays with demonstrated I-V properties show that monolithic integration of HgCdTe-based infrared focal plane arrays on Si read-out integrated circuits is feasible and could be implemented in the 3<sup>rd</sup> generation of infrared systems.
P<sup>+</sup>-v-N<sup>+</sup> structures with HgTe/CdTe superlattice absorber regions were grown by MBE to give cut-off wavelengths in the very long wavelength infrared (14 μm and longer) at temperatures below 80 K. The superlattice period of one sample was 98.3Å according to its x-ray diffraction profile, very close the intended 98.5Å for a 48.5Å HgTe/50.Å Hg<sub>0.05</sub>Cd<sub>0.95</sub>Te superlattice. The cut-off wavelengths of another sample were approximately 14 and 18 μm at 77 and 40K, respectively, as determined by optical absorption and spectral response measurements. A first batch of devices annealed at 150°C or 180°C for 1 hr after the deposition of 50Å thick gold films showed relatively low R<sub>0</sub>A values (approximately 0.3 ohm-cm<sup>2</sup>). This was interpreted to be due to the formation of a junction near the boundary of the superlattice and a high carrier concentration region of HgCdTe alloy. A second batch of devices was annealed at 120°C for 1 hr or 5 min. to decrease the gold diffusion depth. The electrical properties showed higher R<sub>0</sub>A values (approximately 8 ohm-cm<sup>2</sup>). The detectivities of the second batch devices at 77K were in the range of 10<sup>8</sup> to 10<sup>10</sup> cmHz½/W and showed frequency dependence because the noise had frequency dependence. We observe very low knee frequencies (below 10Hz) in their noise spectra.
The narrow gap semiconductor HgCdTe is commonly used for IR detection. Conventional HgCdTe IR detectors need significant cooling in order to reduce noise and leakage currents resulting from thermal generation and recombination processes. These cooling requirements considerably increase the cost, size, weight and complexity of infrared systems. The need for cooling to reduce noise and leakage currents resulting from Auger processes has long been thought to be fundamental and inevitable. However, recently, it has been suggested that by means of a steady-state non-equilibrium mode of operation, which holds the carrier densities below their equilibrium values, Auger generation and even radiative generation rates can be reduced. This is possible through the reduction of carrier concentrations because the Auger generation rate depends approximately on the square of the carrier concentration and radiative recombination rate depends linearly on it. This paper reports the modeling of a HgCdTe detector operated in a steady-state non-equilibrium mode at 230 approximately equals 295 K. The device architecture, NvP<SUP>+</SUP>, which is practical in MBE growth, is suitable for this application. Radiative and Auger lifetimes, zero surface recombination velocities, and zero background photon fluxes are assumed. The dependence of detectivity on minority carrier extraction efficiency is studied in this paper. At 230 and 250 K for N<SUB>D</SUB> equals 1 X 10<SUP>14approximately equals 15</SUP> cm<SUP>-3</SUP>, the detectivity appears to become saturated at values in the order of 10<SUP>10</SUP> cm Hz<SUP>1/2</SUP>/W when the minority carrier extraction efficiency is greater than 3.
Two different effects of annealing, 1) on the arsenic activation in the in-situ doped mercury cadmium telluride (HgCdTe) layers grown on silicon substrates by molecular beam epitaxy (MBE) and 2) on the CdTe passivant-HgCdTe interface leading to significant changes in the characteristics of metal-insulator-HgCdTe (MIS) and planar photovoltaic (PV) detectors are discussed here. On the arsenic activation, highly compensated n-type properties to 100 percent activation of arsenic up to a total arsenic concentration of 1-2 X 10<SUP>18</SUP> cm<SUP>-3</SUP> and a decrease in activation thereafter are observed for annealing temperatures in the range of 235 to 450 degrees C. A range of annealing effects varying from unidentified structural defects acting as donors, probably due to donor arsenic tetramers or donor tetramers or donor tetramer clusters at 235 degrees C, to dissociation of bonds of neutral arsenic tetramer clusters to enable arsenic to occupy Te sites and behave as acceptors at 450 degrees C, are invoked to explain the arsenic activation mechanisms. The activation annealing, on the other hand, was found to have detrimental effect on the passivant-HgCdTe interface, possibility due to mercury diffusion during post-implant annealing. Capacitance-Voltage of MIS devices and current-voltage characteristics of planar diodes show tunneling limited performance with in-situ grown CdTe after annealing and show dramatic improvement in the performance characteristics when the in-situ grown CdTe is chemically removed and fresh CdTe passivation layer grown by MBE after arsenic activation annealing. Test structures containing mini arrays of square diodes with variable areas from 5.76 X 10<SUP>-6</SUP> cm<SUP>2</SUP> to 2.5 X 10<SUP>-3</SUP> cm<SUP>2</SUP> and MIS devices are used to establish the aforementioned effect. Under optimized conditions, state-of- the-art performance of the diodes in the mid-wavelength IR region with dynamic impedance on the order of 10<SUP>7</SUP> Ohm- cm<SUP>2</SUP> is demonstrated.
In this paper, we report the capacitance-voltage (C-V) properties of metal-insulator-semiconductor (MIS) devices on CdTe/HgCdTe by the metalorganic chemical vapor deposition (MOCVD) and CdZnTe/HgCdTe by thermal evaporation. In MOCVD, CdTe layers are directly grown on HgCdTe using the metal organic sources of DMCd and DiPTe. HgCdTe layers are converted to n-type and the carrier concentration, N<SUB>D</SUB> is low 10<SUP>15</SUP> cm<SUP>-3</SUP> after Hg-vacancy annealing at 260 degrees Celsius. In thermal evaporation, CdZnTe passivation layers were deposited on HgCdTe surfaces after the surfaces were etched with 0.5 - 2.0% bromine in methanol solution. To investigate the electrical properties of the MIS devices, the C-V measurement is conducted at 80 K and 1 MHz. C-V curve of MIS devices on CdTe/HgCdTe by MOCVD has shown nearly flat band condition and large hysteresis, which is inferred to result from many defects in CdTe layer induced during Hg-vacancy annealing process. A negative flat band voltage (V<SUB>FB</SUB> approximately equals -2 V) and a small hysteresis have been observed for MIS devices on CdZnTe/HgCdTe by thermal evaporation. It is inferred that the negative flat band voltage results from residual Te<SUP>4+</SUP> on the surface after etching with bromine in methanol solution.
The capacitance-voltage (C-V) and the Hall effect measurements were used, in order to study electron cyclotron resonance (ECR) plasma damage in HgCdTe (MCT). In this study using ECR treatments of MCT and C-V measurements, we observed that the type conversion of MCT surface largely depended on the ECR etching conditions, when MCT was etched by ECR plasma as a function of the ECR power and dc bias. The n-type conversion was not observed when the p-type MCT was etched under the condition of ECR power 150 W and dc bias -20 V. As dc bias of ECR increased over -40 V at the constant ECR power 150 W, the p-type MCT was converted to n-type. The p-type MCT was also converted to n-type when ECR power increased to 500 W at the constant dc bias -20 V. These results probably were due to the inter-diffusion of a large amount of excess mercury, liberated during the ECR treatment, into MCT, which were similar to the results of ion milling process. Another interesting result, observed in C-V measurements, was the p- type conversion from n-type MCT when the n-type MCT was etched under the condition of ECR power 150 W and dc bias -20 V. As dc bias of ECR increased over -40 V, the C-V curve was the results of n-type MCT characteristics. We considered that a low dc bias of -20 V, the hydrogen passivation and the deficiency of mercury in the etched surface were dominant and resulted in conversion to p-type. As dc bias increased over -40 V, the inter-diffusion of excess mercury into MCT was dominant and associated with keeping the n-type characteristics.