Defect inspection is a challenge in the edge of wafer region and several new inspection tools and techniques have come
to the market to fulfill this inspection need. Current inspection methodology excludes inspection of partial die located at
the wafer edge, which has lead to the development of a technique available for patterned wafer inspection tools to inspect
these partially printed die. In this paper we identify and develop a robust methodology for the characterization and
monitoring of defectivity on the partially printed edge die. The methodology includes the development of methods for
inspection optimisation requirements, characterization and isolation of defect sources, optimisation of clustering and
binning and control of partial die defectivity.
Minute variations in advanced VLSI manufacturing processes are well known to
significantly impact device performance and die yield. These variations drive the need
for increased measurement sampling with a minimal impact on Fab productivity.
Traditional discrete measurements such as CDSEM or OCD, provide, statistical
information for process control and monitoring. Typically these measurements require a
relatively long time and cover only a fraction of the wafer area.
Across array across wafer variation mapping ( AWV) suggests a new approach for high
throughput, full wafer process variation monitoring, using a DUV bright-field inspection
tool. With this technique we present a full wafer scanning, visualizing the variation
trends within a single die and across the wafer.
The underlying principle of the AWV inspection method is to measure variations in the
reflected light from periodic structures, under optimized illumination and collection
conditions. Structural changes in the periodic array induce variations in the reflected
light. This information is collected and analyzed in real time.
In this paper we present AWV concept, measurements and simulation results.
Experiments were performed using a DUV bright-field inspection tool (UVision(TM), Applied
Materials) on a memory short loop experiment (SLE), Focus Exposure Matrix (FEM) and
normal wafers. AWV and CDSEM results are presented to reflect CD variations within a
memory array and across wafers.
As the design rule of semiconductor devices shrinks to below 100nm dimensions, the degree of pattern alignment from different process levels has become a crucial factor affecting both process control and induced defect on unit process. Isolated and dense patterns were formed at process layers from front-end through to back-end on wafers using sub 100nm device process utilizing ArF lithography under various lithography conditions. As pattern size is reduced, overlay discrepancies become larger. The OL (overlay) error is very important because the pattern misalignment induces critical defects for the device. For many years, overlay metrology for process control has been measured by 4-corner box-in-box methods in chip. OL errors and CD (Critical Dimension) values have been measured on different tool. CD values have been measured on SEMs (Scanning Electron Microscope) and OL errors have been measured on optical tools. The accuracy of OL error metrology is limited by the resolution of tool, which is on the order of 1μm. In this paper we calculated the degree of overlay errors (current level to prior level errors) through a process patterns images obtained from a CD-SEM.
Proc. SPIE. 5752, Metrology, Inspection, and Process Control for Microlithography XIX
KEYWORDS: Electronics, Sensors, Electron microscopes, Control systems, Image analysis, Scanning electron microscopy, Image quality, Critical dimension metrology, Semiconducting wafers, Electron transport
Contact patterns that have high aspect ratio (HAR) are inevitable as the design rule has been shrunk in semi-conductor fabrication processes. HAR contacts have serious troubles to monitor the Critical Dimension (CD) of the contact bottom images with Scanning Electron Microscope (SEM). Because we can not see the bottom images anymore with general methods as the contact is getting deep. We must be able to extract secondary electrons from the contact bottom to monitor the bottom images in the contact patterns. One possible solution that we may suggest is using positive charges on the wafer surface as a driving force for secondary electrons from the contact bottom. If the positive charges are generated on the wafer surface, an electric field will be created between the contact bottom and the wafer surface. The electric field will drive the secondary electrons from the contact bottom to the wafer surface, which makes the contact bottom images. High surface voltage can be acquired when the electron energy and the magnification in pre-charge are smaller, but it requires longer charging time. High probe current can help the charging time in this case, though it may cause some damages on the wafer. After all, optimized determination is required considering the charging time and the surface voltage at various aspect ratios. In addition, there is one thing that we must consider. When the charged contact pattern is exposed to electrons at high magnification, the surface voltage on the wafer surface tends to be stabilized at lower voltage which causes fading away of the contact bottom images. Therefore, electron exposure must be minimized at high magnification by setting the focus a little away from the observation point and so on.
As the design rules of semiconductor devices continue to decrease, the detection of critical killer defects has become more difficult. In this paper, μ-bridge defects are studied. In order to detect special μ-bridges, both direct inspection and simulation techniques were employed. The inspection technologies used include brightfield, darkfield, and electron-beam inspection (EBI) tools, while the simulation analysis uses charge calculations and Monte Carlo scattering simulation. Special μ-bridge defects were only captured by the EBI tool and verified by focused ion beam (FIB) milling. This result corresponds to simulation data.
The measurement of edge roughness has become a hot issue in the semiconductor industry. Especially the contact roughness is being more critical as design rule shrinks. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. However the features currently available in commercial CD-SEM cannot provide a proper solution in monitoring the contact roughness. We had introduced a new parameter R, measurement algorithm and definition of contact edge roughness to quantify CER and CSR in previous paper. The parameter, R could provide an alternative solution to monitor contact or island pattern roughness. In this paper, we investigated to assess optimum number of CD measurement (1-D) and fitting method for CER or CSR. The study was based on a circular contact shape. Some new ideas to quantify CER or CSR were also suggested with preliminary experimental results.
The measurement of edge roughness has become a hot issue in the semiconductor industry. Major vendors offer a variety of features to measure the edge roughness in their CD-SEMs. However, most of the features are limited by the applicable pattern types. For the line and space patterns, features such as Line Edge Roughness (LER) and Line Width Roughness (LWR) are available in current CD-SEMs. The edge roughness is more critical in contact process. However the measurement of contact edge roughness (CER) or contact space roughness (CSR) is more complicated than that of LER or LWR. So far, no formal standard measurement algorithm or definition of contact roughness measurement exists. In this article, currently available features are investigated to assess their representability for CER or CSR. Some new ideas to quantify CER and CSR were also suggested with preliminary experimental results.
Traditionally the defects, detected by inspection tools (optic & EBI), have been reviewed through DR-SEM or CD-SEM. Nevertheless, when physical defects are characterized using conventional in-line SEM it is hard to re-detect electrical defects because of the restricted working range in e-beam control. To detect and review electrical defects on contact layer EBI tools were used due to the in-line SEM limitation on electrical defect reviews. However the quality of the image was not acceptable to characterize type of defects due to its low resolution (20~30nm). In this article, the review condition of electrical defect was studied under the various electric conditions on Self Align Contact (SAC) layer. In order to achieve the optimum condition, a wide range of negative and positive conditions were applied using acceleration voltage, I-probe current, cap voltage and scan rate. Under stable weak negative charge conditions, 100% review of electrical and contact bottom defects were achieved. Furthermore, we found the high I-probe current and the appropriate acceleration voltage are main factors which increase the capability to re-detect the electrical defect. In this article, we figure out which defect is electrical defect and non-electrical defect applying to diverse electric conditions on the wafer.