Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implant layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build.
In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.
As design rule of devices are getting smaller, it is hard to obtain enough process window like DOF, EL. In aspect of
device integration, lithography processes which are included in etching process became more and more important. It has
been claimed that photo resist profile is closely related with etch bias and vertical profile. Resist top-loss and bottom
slope seriously affect after-etching profile. In order to address these problems, new model based verification method is
necessary for preventing hot spots.
In this paper, we propose more practical method of model based verification using rigorous simulation and wafer
verification results. Highly accurate model is obtained by physical model fitting with minimal experimental data set.
After that, virtual data are extracted from rigorous simulation model for applying full chip model based verification
modeling. Basically, 2 data sets will be needed for verification of 2-level model, for detecting resist top-loss and bottom-slope.
Finally this article shows comparison results of model based verification and real wafer inspection. And also, we
try to prove that the newly proposed method is another good candidate to address existing problems such as pinching and
bridging after post etching and CMP process.
The study of OPC (Optical Proximity Correction) model that well predict the wafer result has been
researched. As the pattern design shrink down, the need for the CD (Critical Dimension) controllability
increased more than before. To achieve these requirements, OPC models must be accurate for full chip
process and model inaccuracies are one of several factors which contribute to errors in the final wafer image.
For that reason, robust OPC using real lithographic terms was proposed. Real lithographic system is quite
different from ideal system that is used for OPC modeling. Until now, this difference was acceptable since
pattern size used for OPC model was large, but as device size shrinks, this gap between ideal and real system
causes degradation of OPC accuracy. So, various optical parameters such as apodization, laser band width,
degree of polarization, illumination are used today in order to compensate for this issue. Especially, major
issue in modeling error is related to how the illumination source is used. For this study we assess accuracy of optical model for robust OPC using ideal and actual illumination
sources, and test conditions are as follows: 1) We examined the difference of pupil types to output model respectively; 2) A parameterized test pattern layout was used by 1D test pattern types that have various lines and spaces; 3) All models were calculated in automation method so as to exclude the dependency of user skills; 4) OPC accuracies were examined by gate layer patterns on full chip level. The study is performed for 5X~4Xnm nodes lithographic processes. The main focus of the study was on usability of model that is made by measured source data in semiconductor manufacturing. Results clearly showed that the actual source for the optical model has merits and demerits.
Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory
industries including DRAM and NAND Flash business have driven much finer technology to improve
productivity. Polarization at hyper NA has been well known as important optical technology to enhance
imaging performance and also achieve very low k1 process. The source polarization on dense structure has
been used as one of the major RET techniques. The process capabilities of various layers under specific
illumination and polarization have been explored.
In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE
(Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and
investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization
Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation
will be done to estimate the CD variation impact of each polarization to different illumination. Third, various
line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see
the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and
future work will be discussed.
In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and
the guidelines for polarization control is discussed based on the patterning performances.
In resolution limited lithography process, the contact hole pattern is one of the most challenging features to be printed on wafer. A lot of lithographers struggle to make robust hole patterns under 45nm node, especially if the contact hole patterns are composed of dense array and isolated hole simultaneously. The strong OAI(Off Axis Illumination) such as dipole is very useful technique to enhance resolution for specific features. However the contact hole formed by dipole illumination usually has elliptical shape and the asymmetric feature leads to increment of chip size.
In this paper, we will explore the lithographic feasibility for the coexisting dense array with isolated contact holes and the technical issues are investigated to generate finer contact hole for both dense and isolated feature. Conventional illumination with resist shrinkage technique will be used to generate dense array and isolated contact hole maintaining original shape for the sub-50nm node memory device.
The contact hole patterning has been huge challenge in the photolithography since sub-100nm node device. There are many difficulties for NA (Numerical Aperture) and illumination optimization, especially since dense and sparse contact holes are mixed in the same mask. The high NA and OAI (Off Axis Illumination) have strong improvements for pattern fidelity and process margin in case of dense contact holes but DoF (Depth of Focus) margin is a problem for sparse patterns. The lithography engineers have two ways to overcome these contact holes patterning problems. The one is using the resist techniques such as resist thermal flow, SAFIER (Shrink Assist Techniques for Enhanced Resolution), RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) and the other is optimizing illumination and mask layout such as SRAF (Sub Resolution Assist Feature), OAI and PSM (Phase Shift Mask), double exposure. This paper will discuss contact hole patterning results using a combination OAI and SRAF with KrF.
95nm KrF lithography has been developed for 512 Mb DRAM. KrF 0.80NA scanner was used to print 190nm pitch patterns and this means the process factor k1 is 0.306. Crosspole illumination was used to print critical layers, which has four poles on x and y-axis. To improve CD uniformity of critical layers we also used fogging effect corrected (FEC) reticles and thin photo resist process, which needs the hard mask etching process to overcome poor dry etch resistance. For 95nm DRAM cell patterns, we could get more than 8% exposure latitude (EL) and 0.3 μm depth of focus (DOF). With FEC masks and optimized resist process, CD uniformity of word line layer printed on wafer was less than 10nm. Overlay accuracy of critical layers is mostly less than 25nm. However at core and periphery area of DRAM the extreme off-axis illumination like crosspole brought poor process latitude in weak zone duties and therefore the hard optical proximity correction (OPC) work was required. In a real integration other novel technologies are used such as gap-filling for STI and ILD processes, Wsi gate, W bit line and SAC processes. This paper reported only lithographic performance for printing 95nm DRAM patterns. Consequently KrF lithography is still promising technology to print sub 100nm node DRAM.
248nm wave lithography process is being pushed and extended to sub 130nm node by continuous RET(Resolution Enhancement Technique) improvement. By applying various kind of RET such as exposure lens NA(Numerical Aperture) enlargement, more strong OAI(Off Axis Illumination), elaborated OPC(Optical Proximity Correction), and high performance resist, we still can’t give up for 248nm wave technology 130nm node and beyond. But there are some major challenges to reduce MEEF(Mask Error Effect Factor) and understand lens aberrations. This paper will try to find out mutual relationship between 248nm 0.8NA exposure lens aberration and actual patterns. Influence of lens aberration on patterning characteristic will be investigated by using in house simulation tool.
Most chip makers want KrF lithography is extended below sub 100nm lithography due to cost and process stability, even though ArF lithography has been growing and its performance is enough to apply to 100nm node. But process control of KrF lithography will become difficult at sub 100nm node era because of difficulty of mask making, accuracy of optical proximity correction (OPC), lens effects caused by strong off-axis illumination, need more tool accuracies than ever, and so on.
CD Metrology for Avoiding Shrinkage of ArF Resist Patterns in 100nm ArF Lithography
Tae-Jun You, Cheolkyu Bok, Ki-Soo Shin
Hynix Semiconductor, San 136-1 Amiri, Bubal-eub, Ichon-si, Kyongki-do
We have observed CD(Critical Dimension) shrinkage of acrylate type ArF resist patterns during SEM measurement. CD change was 30% shrinkage for line pattern and 10% expansion for contact hole patterns after 30 times measurement. CD shrinkage was proportion to line pattern size but no relation with LER(Line Edge Roughness). We confirm that CD shrinkage different from resist to resist and SEM measurement condition. CD shrinkage was bigger for acrylate type resist than COMA(Cyclo Olefin Maleic Anhydride) type resist and smaller at lower electron voltage and current conditions. In order to get the improvement of CD shrinkage, we performed electron-beam curing before SEM measurement. Above (see paper for formula) electron-beam dose condition, CD shrinkage improved from 10% to 3%. However, this method caused OPC(Optical Proximity Correction) issue as CD also changed after electron-beam curing. Therefore, we tried to develop a new measurement method instead of applying additional process technique. In this paper, we will describe our CD measurement method, Off-Site measurement technique, for 100nm DRAM lithography. The Off-Site CD measurement repeatability (formula available in paper) was controlled below (see paper).
The feasibility of sub-100 nm patterning with ArF lithography has been studied. We used ArF 0.63 NA exposure tool and investigated process windows. In-house resist (DHA-H110) and bottom anti-reflective coating material (HEART004) are used as well as commercial ones. To print sub-100 nm patterns we used the resolution enhancement technology (RET) that is extreme off-axis illumination (OAI) such as dipole and strong annular. To predict the result and compare with experimental data our simulation tool HOST (Hyundai OPC Simulation Tool) based on diffused aerial image model (DAIM) was used. Although the infrastructure of ArF lithography is not mature enough, we got a good result. For 95 nm and 90 nm patterns we could get more than 8% exposure latitude (EL) and 0.3 micrometer depth of focus (DOF). For isolated gate pattern sub-70 nm pattern was printed and we have got the characteristics of 70 nm periphery transistor. For contact hole (C/H) patterns it was more effective to use KrF lithography because resist thermal flow process (RFP) can be used to shrink C/H size. With RFP we printed up to 50 nm C/H patterns. Through this study we found that k1 value can be reduced up to 0.29 and ArF lithography can be applied for 70 nm node with high contrast resist and high NA exposure tool.