This paper investigates the CD correction methods to obtain better across-wafer CD uniformity (CDU) after etching for
logic devices which have various types of patterns. CD optimization methods are evaluated for contact holes with a
diameter of 46 nm after etching. CD optimization methods with PEB temperature and exposure-dose mapping on a wafer
at a lithography step are examined in detail. Simulation study using a full physical resist model is done to analyze the
detailed effects of each optimization method. The results of the simulation show that better optical and chemical image
gives better CD controllability through pitches for etching CD correction. Simulation results also show that the pitch
with a middle CD sensitivity makes the CD correction sensitivity difference minimum through pitches. From the
simulation, the sensitivity behaviors are found to be relatively similar for both of PEB temperature and dose control.
Rather than sensitivity behavior differences between the two CD control methods, the intra-wafer spatial resolution of
the CD control methods is found to be an important factor for the strategy of CD optimization. Finally, by contact-layer
CD optimization, across-wafer CDUs are improved by more than 50%. The variation in the electric resistance of contacts
is also improved by more than 20%. As a result, the proposed method is found to be effective for CDU improvement of
through-pitch contact-hole patterning for advanced logic device.
For 32 nm Node Logic Device, we studied the effect of laser bandwidth variation on Optical Proximity Effect (OPE) by
investigating through-pitch critical dimension (CD) performance. Our investigation evaluated CD performance with and
without the application of Sub-resolution Assist Features (SRAF). These results enabled us to determine the Iso-Dense
Bias (IDB), and sensitivity to laser bandwidth, for both SRAF and no-SRAF cases, as well as the impact on Process
Window. From the IDB results we present the required laser bandwidth stability in order to maintain OPE variation
within CD Budget tolerances. We also introduce OPE matching results between different generation Immersion
Lithography exposure tools evaluated for 45nm Node Logic Device.