Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field. The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve.
With the advancement of lithography, the overlay budget is becoming extremely tight. As the accuracy of overlay is
important for achieving a good yield, the demand for the accuracy of overlay is ever increasing. According to the
International Technology Roadmap for Semiconductors (ITRS), the overlay control budget for the 32nm technology
node will be 5.7nm. The overlay metrology budget is typically 1/10 of the overlay control budget resulting in overlay
metrology total measurement uncertainty (TMU) requirements of 0.57nm for the most challenging use cases of the 32nm
node. The current state of the art imaging overlay metrology technology does not meet this strict requirement, and further
technology development is required to bring it to this level. Especially for exposure tool inspection (e.g. alignment,
overlay, wafer stage and distortion), more high accuracy should be required using 'resist to resist' pattern.
In this work we simulated the measurement sensitivity for two types of scatterometry based overlay metrology, one is
differential signal scatterometry overlay (SCOL), the other is double exposure type (DET).
We have proposed a new inspection method of in-line focus and dose controls for semiconductor volume production.
We referred to this method as the focus and dose line navigator (FDLN). Using FDLN, the deviations from the optimum
focus and exposure dose can be obtained by measuring the topography of the resist pattern on a process wafer that was
made under a single-exposure condition. Generally speaking, FDLN belongs to the technology of solving the inverse
problem as scatterometry. The FDLN sequence involves following the two steps. Step 1:creating a focus exposure matrix
(FEM) using a test wafer for building the model as supervised data. The model means the relational equation between the
multi measurement results of resist patterns ( e.g. Critical dimension (CD), height, sidewall angle) and FEM's exposure
conditions. Step 2: measuring the resist patterns on a production wafers and feeding the measurement data into the
library to extrapolate focus and dose. To estimate the accuracy of FDLN, we performed some experiments. We
developed a FEM with an ArF lithography tool and measured the resist patterns of the FEM wafer with the advanced
CD-SEM (Critical Dimension-Scanning Electron Microscope). Using the MPPC (Multiple Parameters Profile
Characterization) data from the advanced CD-SEM, we obtained the following results. Focus: 21.5 nm (4.1 nm) and
Dose: 1.5% (2.0 nm). The numerical value in a parenthesis shows the value of the estimated accuracy with changing CD.
We also show other experimental results in this paper and the application of the focus and dose controls for
semiconductor exposure tool.
In lithography, the alignment error can be categorized into three factors. The first factor is called as Tool Induced Shift (TIS). The second is Wafer Induced Shift (WIS) and the third is the interaction between TIS and WIS. About TIS, we have defined a new evaluation criterion. About WIS, we have shown an error analyzer to quantify and compensate the alignment error using Atomic Force Microscope (AFM) and optical simulation. We have called this analyzer as 'Alignment Offset Analyzer'. This analyzer has the following
features. The topography of an alignment mark and resist surface on the alignment mark are measured individually by the AFM. The two topography data are wrapping over in a signal simulator. Using the wrapped topography, an alignment signal and an alignment measurement offset are calculated. Since the alignment offset can also be calculated before exposure sequence, the alignment offset can be inputted to exposure tool without send-ahead wafers. This time we report the accuracy of the Alignment Offset Analyzer. The alignment offset measured by an exposure tool and the calculated one above mentioned showed a good agreement, and the difference was several nm.
Alignment error that originates in the actual wafer process is one of the factors to deteriorate total overlay accuracy. This error has been called wafer induced shift (WIS). WIS occurs through a change of alignment marks topography under the actual wafer processing. To quantify mark asymmetry WIS, we study the mark asymmetry on tungsten chemical mechanical polishing (CMP) wafers by using an atomic force microscope and define new criterion in this paper. The mark topography of CMP process wafers are measured by AFM and quantified using the new criterion. The asymmetry of the mark topography can be quantified by measuring the profiles of an alignment mark across the wafers. It has been proven, that the rotation error is caused by the asymmetry of the mark topography and the asymmetry is not related to the line width of the mark.
KEYWORDS: Semiconductors, Error analysis, Tungsten, Signal processing, Chemical analysis, Optical alignment, Semiconducting wafers, Overlay metrology, Near field optics, Chemical mechanical planarization
Alignment error that originates in the actual wafer process is one of the factors that deteriorates total overlay accuracy. This error is known as wafer induced shift (WIS). WIS occurs through a change of alignment mark topography during the actual wafer processing. To reduce this error, we propose a tool that will simulate an alignment offset generated by WIS. We have called this tool the Alignment Offset Analyzer. The Alignment Offset Analyzer consists of a profiler for measuring the alignment mark topography and a simulator that simulates the alignment offset. By using the Alignment Offset Analyzer, we simulate the alignment signals from a Tungsten chemical mechanical polishing (CMP) wafer. The simulated alignment signals have an asymmetric shape due to the wafer processing. With these signals, the alignment offset caused by WIS can be estimated prior to the exposure sequence.