We report the development of a 2-million-pixel, that is, a 2000 x 1000 array format, SOI diode uncooled IRFPA with 15
μm pixel pitch. The combination of the shrinkable 2-in-1 SOI diode pixel technology, which we proposed last year ,
and the uncooled IRFPA stitching technology has successfully achieved a 2-million-pixel array format. The chip size is
40.30 mm x 24.75 mm. Ten-series diodes are arranged in a 15 μm pixel. In spite of the increase to 2-million-pixels, a
frame rate of 30 Hz, which is the same frame rate as our former generation (25 μm pixel pitch) VGA IRFPA, can be
supported by the adoption of readout circuits with four outputs. NETDs are designed to be 60 mK (f/1.0, 15 Hz) and 84
mK (f/1.0, 30 Hz), respectively and a τ<sub>th</sub> is designed to be 12 msec. We performed the fabrication of the 2-million-pixel
SOI diode uncooled IRFPAs with 15 μm pixel pitch, and confirmed favorable diode pixel characteristics and IRFPA
operation where the evaluated NETD and τ<sub>th</sub> were 65 mK (f/1.0, 15 Hz) and 12 msec, respectively.
Scalable new SOI diode structure has been proposed and developed for beyond 17μm pixel pitch mega-pixel-class SOI
diode uncooled infrared focal plane arrays (IRFPAs). Conventionally, each p<sup>+</sup>n vertical diode is formed between a p<sup>+</sup>diffusion and an n-body in each SOI active area, and 8-10 diodes are serially connected with interconnections. In the
proposed new structure, we employ two kinds of diodes, namely, p<sup>+</sup>n and n<sup>+</sup>p vertical diodes. First, two regions of an nbody
and a p-body are prepared in an SOI active area. In the n-body, a p<sup>+</sup> diffusion is formed apart from the n-body /pbody
boundary. In the p-body, an n+ diffusion is formed apart from the boundary. In this way, a p<sup>+</sup>n vertical diode and an
n+p vertical diode are formed together in an SOI active area. Moreover, a contact hole, which is formed in touch with
both n- and p-bodies, electrically connects these two kinds of diodes. With this new structure which is named "new 2-in-
1 SOI diode structure", we have realized remarkable reduction of the diode area. It leads to significant increase of the
diode series number in a pixel, which increases infrared responsivity of the pixel. As a result, designing a 15μm pixel
pitch IRFPA with the new structure, 12 series diodes can be arranged in a pixel, although 10 series diodes have been
used even in the case of our 25μm pitch generation pixel.
To confirm the ability of the new diodes, test elements of 12-17μm pitch pixels were fabricated and evaluated.
Furthermore, the fabrication of 17μm pixel pitch 320 x 240 IRFPAs with the new diodes was carried out and their
favorable FPA operations were successfully verified.
In conclusion, the proposed and developed new SOI diode technology is very promising for beyond 17μm pixel pitch
mega-pixel-class uncooled IRFPAs.
We have developed a novel readout circuit architecture realizing a TEC-less (Thermo-Electric Cooler) operation for an
SOI diode uncooled infrared focal plane array (IRFPA). Through the fabrication of an SOI diode uncooled 320 x 240
IRFPA adopting the readout circuit architecture with our existing 25μm pixel-pitch technology, we demonstrate that the
variation of the output DC level of the pixels is successfully suppressed in environmental temperatures from -10°C to
50°C. The developed TEC-less technology greatly enhances the ability of the SOI diode uncooled IRFPA, which
inherently possesses excellent uniformity and low noise features.