Mr. Takahisa Otsuka Profile

Takahisa Otsuka

at Tokyo Electron Kyushu Ltd

SPIE Involvement:

Author

Publications (7)

Proceedings Article | 31 March 2010 Paper

Topcoat-less resist process development for contact layer of 40nm node logic devices

Masafumi Fujita, Takayuki Uchiyama, Tetsunari Furusho, Takahisa Otsuka, Katsuhiro Tsuchiya

Proceedings Volume 7639, 763923 (2010) https://doi.org/10.1117/12.846270

KEYWORDS: Photoresist processing, Logic devices, Semiconducting wafers, Lithography, Immersion lithography, Thin film coatings, Yield improvement, Resistance, Electronics, Scanners

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Proceedings Article | 1 April 2009 Paper

Improvements in process performance for immersion technology high volume manufacturing

K. Nafus, T. Shimoaoki, M. Enomoto, H. Shite, T. Otsuka, H. Kosugi, T. Shibata, J. Mallmann, R. Maas, C. Verspaget, E. van der Heijden, E. van Setten, J. Finders, S. Wang, N. Boudou, C. Zoldesi

Proceedings Volume 7273, 727338 (2009) https://doi.org/10.1117/12.813485

KEYWORDS: Semiconducting wafers, Particles, Scanners, Critical dimension metrology, Photomicroscopy, Photoresist processing, Contamination, Etching, Polymers, Bridges

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Proceedings Article | 4 April 2008 Paper

Process manufacturability evaluation for next generation immersion technology node

M. Enomoto, T. Shimoaoki, T. Otsuka, S. Hatakeyama, K. Nafus, R. Naito, Y. Terashita, T. Shibata, H. Kosugi, M. Jyousaka, J. Mallmann, R. Maas, M. Blanco Mantecon, E. van Setten, J. Finders, S. Wang, C. Zoldesi

Proceedings Volume 6923, 69231W (2008) https://doi.org/10.1117/12.772552

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Manufacturing, Inspection, Standards development, Scanners, Bridges, Particles, Metrology, High volume manufacturing

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Proceedings Article | 4 April 2008 Paper

Process-induced bias: a study of resist design and process implications

Carlos Fonseca, Steven Scheer, Michael Carcasi, Tsuyoshi Shibata, Takahisa Otsuka

Proceedings Volume 6923, 692327 (2008) https://doi.org/10.1117/12.773187

KEYWORDS: Diffusion, Semiconducting wafers, Critical dimension metrology, Photoresist processing, Temperature metrology, Scanners, Calibration, Etching, Logic, Optical proximity correction

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Proceedings Article | 27 March 2007 Paper

CDU minimization at the 45-nm node and beyond: optical, resist, and process contributions to CD control

Steven Scheer, Mike Carcasi, Tsuyoshi Shibata, Takahisa Otsuka

Proceedings Volume 6520, 65204H (2007) https://doi.org/10.1117/12.711822

KEYWORDS: Critical dimension metrology, Monte Carlo methods, Semiconducting wafers, Photoresist processing, Lithography, Temperature metrology, Etching, Scanners, Process control, Reticles

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Proceedings Article | 29 April 2004 Paper

CD error budget analysis in ArF lithography

Takahisa Otsuka, Kazuo Sakamoto

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.534582

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Line width roughness, Error analysis, Diamond patterning, Lithography, Scanning electron microscopy, Photomasks, Photoresist processing, Electron beams

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Proceedings Article | 24 July 2002 Paper

Novel development method for CD control: optimized spin-off development method

Kazuo Sakamoto, Akira Nishiya, Kentarou Yamamura, Takahisa Otsuka

Proceedings Volume 4690, (2002) https://doi.org/10.1117/12.474279

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Cadmium, Diffusion, Liquids, Optical lithography, Deep ultraviolet, Lead

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Showing 5 of 7 publications

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