ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF
dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching
of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the
immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry
resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for
protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity
in mass production of immersion lithography.
In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is
important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer.
We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after
development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into
conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob
defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse, which
was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect
reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.
Through collaborative efforts ASML and TEL are continuously improving the process performance for the
LITHIUS Pro <i>-i/</i> TWINSCAN XT:1900Gi litho cluster. In previous work from this collaboration, TEL and ASML
have investigated the CDU and defectivity performance for the 45nm node with high through put processing.
CDU performance for both memory and logic illumination conditions were shown to be on target for ITRS roadmap
specifications. Additionally, it was shown that the current defect metrology is able to measure the required defect size
of 30nm with a 90% capture rate. For the target through put of 180wph, no added impact to defectivity was seen from
the multi-module processing on the LITHIUS Pro <i>-i</i>, using a topcoat resist process. For increased productivity, a new
bevel cut strategy was investigated and shown to have no adverse impact while increasing the usable wafer surface.
However, with the necessity of double patterning for at least the next technology node, more stringent requirements are
necessary to prevent, in the worst case, doubling of the critical dimension variation and defectivity.
In this work, improvements in process performance with regards to critical dimension uniformity and defectivity are
investigated to increase the customer's productivity and yield for whichever double patterning scheme is utilized.
Specifically, TEL has designed, evaluated and proven the capability of the latest technology hardware for post exposure
bake and defect reduction. For the new post exposure bake hardware, process capability data was collected for 40nm
CD targets. For defectivity reduction, a novel concept in rinse technology and processing was investigated on
hydrophobic non top coat resists processes. Additionally, improvements to reduce micro bridging were evaluated.
Finally bevel rinse hardware to prevent contamination of the immersion scanner was tested.
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose and/or PEB temperature, have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation.
The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.
In order to prepare for the next generation technology manufacturing, ASML and TEL are investigating the process
manufacturability performance of the CLEAN TRACK<sup>TM</sup> LITHIUS Pro<sup>TM</sup>-<i>i</i>/ TWINSCAN<sup>TM</sup> XT:1900Gi lithocluster at
the 45nm node. Previous work from this collaboration showed the feasibility of 45nm processing using the LITHIUS<sup>TM</sup>
<i>i</i>+/TWINSCAN XT:1700i. <sup>1</sup> In this work, process performance with regards to critical dimension uniformity and
defectivity are investigated to determine the robustness for manufacturing of the litho cluster. Specifically, at the spinner
and PEB plate configuration necessary for the high volume manufacturing requirement of 180 wafers per hour, process
data is evaluated to confirm the multi-module flows can achieve the required process performance. Additionally, an
improvement in the edge cut strategy necessary to maximize the usable wafer surface without negative impact to defectivity is investigated.
As the industry transitions to the 45 nm node and beyond, requirements for critical dimension (CD) control
are getting extremely aggressive. Current 45 nm node specifications call for 2 nm or better CD uniformity
(CDU) on the gate level. For critical dimension control in this regime all measurable process effects must
be closely monitored and controlled. This includes such effects as etch uniformity, scanner dose and focus
consistency, post-exposure bake (PEB) plate uniformity, and incoming wafer variation such as wafer
warpage. The problem is that as the number of significant contributors to CDU continues to increase; the
number of parameters that can be used to control CDU has not.
To better understand how to achieve these increasingly stringent CDU targets, the authors have explored
how exposure and resist processing effects CD control. The goal of this work is to simulate how process
parameters such as dose and PEB temperature can be used to effectively control CD, while minimizing
unintended negative effects on thru pitch CD performance, MEEF, and other lithography process metrics.
In addition to traditional lithography metrics, the effect these process changes have on CDU is simulated
using a Monte Carlo technique.
As for CD (Critical Dimension) control, we classified factors of CD variations in each process. We quantified the factors occurred in the devices such as exposure tool, coater/developer and CD-SEM in 193nm lithography. In the coater/developer, influence of PEB (Post Exposure Bake) on CD variation was notably found and made up about 70% of the Track-related factors. This fact indicates that a great importance of PEB in 193nm process. Regarding the exposure tool, we quantified the CD variations caused by Flare using Kirk method. We determined that this issue was influenced by the exposure field layout, and the variation of intra wafer was 1.58nm. As for a CD-SEM, we measured the CD variations caused by the electron beam-induced CD shrink, and LWR (Line Width Roughness). The LWR accounts for about 40% of the total measurement errors, and affects CD variations higher as finer line pattern. We reduced influence of LWR on CD variations by extending measurement points and averaging. Thus we acquired the CD uniformity close to the actual CD.
A loading effect in particular is accounting for an increasing percentage of factors responsible for CD variations. A multi-puddle method in development process therefore is considered a solution of this problem. However, the method consumes large amounts of developer solution. In this paper, we have studied the influence of loading effect on CD and evaluated several development methods to minimize the influence. In this paper, we evaluated the correlation between the width of exposed area and CD in the device area. Based on this result, we estimated the diffusion range of dissolution products. We also found another phenomenon that CD uniformity within a wafer became worse when each pattern was surrounded by an unexposed area. A novel development method we have evaluated in this study is as follows: (1) perform a puddle formation normally; (2) after a short static development, spin off developer solution from the puddle; and (3) after the puddle is decreased in volume, perform a rather long static development. This new method proved to have the capability of minimizing the influence of dissolution products.