Mr. Takashi Murakami Profile

Takashi Murakami

at NEC Corp

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Author

Publications (4)

Proceedings Article | 1 April 2009 Paper

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Seiji Nagahara, Kazuhiro Takahata, Seiji Nakagawa, Takashi Murakami, Kazuhiro Takeda, Shinpei Nakamura, Makoto Ueki, Masaki Satake, Tatsuhiko Ema, Hiroharu Fujise, Hiroki Yonemitsu, Yuriko Seino, Shinichiro Nakagawa, Masafumi Asano, Yosuke Kitamura, Takayuki Uchiyama, Shoji Mimotogi, Makoto Tominaga

Proceedings Volume 7273, 72733A (2009) https://doi.org/10.1117/12.813498

KEYWORDS: Resolution enhancement technologies, Logic, Optical lithography, Line width roughness, Photoresist processing, Lithography, Photomasks, Copper, Diffusion, Logic devices

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Proceedings Article | 16 March 2009 Paper

Feasibility of ultra-low k1 lithography for 28nm CMOS node

Shoji Mimotogi, Kazuhiro Takahata, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Masaki Satake, Yosuke Kitamura, Tomoko Ojima, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Hiroki Yonemitsu, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyoh, Hideaki Harakawa, Akiko Nomachi, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Makoto Tominaga, Soichi Inoue

Proceedings Volume 7274, 72741F (2009) https://doi.org/10.1117/12.814040

KEYWORDS: Lithography, Photomasks, Lithographic illumination, Binary data, Scanners, SRAF, Logic devices, Optical lithography, Metals, Semiconductors

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Proceedings Article | 4 December 2008 Paper

Patterning performance of hyper NA immersion lithography for 32nm node logic process

Kazuhiro Takahata, Masanari Kajiwara, Yosuke Kitamura, Tomoko Ojima, Masaki Satake, Hiroharu Fujise, Yuriko Seino, Tatsuhiko Ema, Manabu Takakuwa, Shinichiro Nakagawa, Takuya Kono, Masafumi Asano, Suigen Kyo, Akiko Nomachi, Hideaki Harakawa, Tatsuya Ishida, Shunsuke Hasegawa, Katsura Miyashita, Takashi Murakami, Seiji Nagahara, Kazuhiro Takeda, Shoji Mimotogi, Soichi Inoue

Proceedings Volume 7140, 714017 (2008) https://doi.org/10.1117/12.804739

KEYWORDS: Resolution enhancement technologies, Optical lithography, Logic, Lithography, SRAF, Metals, Immersion lithography, Semiconductors, Optical proximity correction, Logic devices

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Proceedings Article | 22 March 2008 Paper

Improvement of gate CD uniformity for 55 nm node logic devices

Takashi Murakami, Taisaku Nakata, Kensuke Taniguchi, Takayuki Uchiyama, Megumi Jyousaka, Masahide Tadokoro, Yoshitaka Konishi

Proceedings Volume 6922, 692210 (2008) https://doi.org/10.1117/12.771548

KEYWORDS: Critical dimension metrology, Etching, Lithography, Logic devices, Temperature metrology, Electronics, Reticles, Semiconducting wafers, Control systems, Chemical vapor deposition

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