Mr. Takehiko Iwanaga Profile

Takehiko Iwanaga

at Canon Inc

SPIE Involvement:

Author

Publications (11)

Proceedings Article | 21 September 2020 Presentation

Computational lithography and its role in nanoimprint lithography for semiconductor device manufacturing

Toshiya Asano, Junichi Seki, Yuichiro Oguchi, Naoki Kiyohara, Koshiro Suzuki, Kohei Nagane, Hiromi Hiura, Keita Sakai, Mitsuru Hiura, Osamu Morimoto, Yukio Takabayashi, Takehiko Iwanaga

Proceedings Volume 11518, 115180V (2020) https://doi.org/10.1117/12.2574629

KEYWORDS: Nanoimprint lithography, Photomasks, Manufacturing, Optical lithography, Stochastic processes, Computational lithography, Semiconductor manufacturing, Semiconductors, Photoresist processing, Ultraviolet radiation

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Proceedings Article | 23 March 2020 Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Atsushi Kimura, Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Keita Sakai, Hiroshi Morohoshi, Toshiya Asano, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 11324, 113240B (2020) https://doi.org/10.1117/12.2551985

KEYWORDS: Nanoimprint lithography, Semiconducting wafers, Optical alignment, Photomasks, Distortion, Overlay metrology, Optical lithography, Wafer testing, Lithography, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results. On test wafers, XMMO of 3.2nm and 2.8nm in x and y respectively was demonstrated. There is also an opportunity to further improve results by applying wafer chucks with better flatness specifications. Further advances have also been made through the application of a multi-wavelength alignment strategy. Finally, we discuss how computational methods can enhance NIL productivity and reduce the number of learning cycles

Proceedings Article | 26 September 2019 Presentation + Paper

Patterning, mask life, throughput and overlay improvements for high volume semiconductor manufacturing using nanoimprint lithography

Osamu Morimoto, Takehiko Iwanaga, Yukio Takabayashi, Keita Sakai, Wei Zhang, Anshuman Cherala, Se-Hyuk Im, Mario Meissl, Jin Choi

Proceedings Volume 11148, 111480M (2019) https://doi.org/10.1117/12.2535912

KEYWORDS: Photomasks, Optical lithography, Nanoimprint lithography, Stochastic processes, Semiconductor manufacturing, Particles, Semiconducting wafers, Lithography, Manufacturing equipment, Capillaries

Read Abstract +

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, we review progress on pattern capability, throughput, mask life and overlay. To minimize distortion and improve overlay, a Drop Pattern Compensation (DPC) method has been implemented to minimize the added overlay distortion terms. In this paper we describe the origins of the out of plane errors, and describe the method used to correct these errors along with some examples. Improvements to both cross matched machine overlay (XMMO) and imprint mix and match overlay (IMMO) are presented.

Proceedings Article | 27 June 2019 Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Toshiya Asano, Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 11178, 111780I (2019) https://doi.org/10.1117/12.2532522

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 27 June 2019 Paper

Status of overlay performance for NIL high volume manufacturing

Tatsuya Hayashi, Yukio Takabayashi, Mitsuru Hiura, Takehiko Iwanaga, Hiroshi Morohoshi, Takamitsu Komaki

Proceedings Volume 11178, 111780J (2019) https://doi.org/10.1117/12.2536315

KEYWORDS: Semiconducting wafers, Distortion, Nanoimprint lithography, Overlay metrology, Photomasks, Wafer testing, Optical alignment, Source mask optimization, Lithography, Optical lithography

Read Abstract +

Nanoimprint lithography (NIL) techniques are known to possess replication resolution below 5nm. A specific form of imprint lithography using jetted resist has been developed for manufacturing advanced CMOS memory. Canon’s NIL process involves field-by-field inkjet deposition of a low viscosity resist fluid followed by imprinting with nano-scale precision overlay. A mask with a relief structure is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is separated from the substrate leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. The linear response of the HODC system was demonstrated for multiple high order terms and on test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was achieved. Additionally an SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications.

Proceedings Article | 26 March 2019 Paper

The advantages of nanoimprint lithography for semiconductor device manufacturing

Keita Sakai, Kiyohito Yamamoto, Hiromi Hiura, Takahiro Nakayama, Toshiya Asano, Tomohiko Hayashi, Yukio Takabayashi, Takehiko Iwanaga, Douglas Resnick

Proceedings Volume 10958, 109580G (2019) https://doi.org/10.1117/12.2514925

KEYWORDS: Photomasks, Nanoimprint lithography, Semiconducting wafers, Lithography, Optical lithography, Manufacturing, Semiconductors, Line width roughness, Particles, Semiconductor manufacturing

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Given the risks associated with this introduction, generally a combination of both performance and cost advantage is preferred. In this paper both performance attributes and cost are discussed. NIL resolution and linewidth roughness do not have the limitations of conventional projection lithographic method. Furthermore, it is not subject to patterning restrictions that forced the industry towards one dimensional patterning. A cost example case of 20nm dense contacts is also presented. Because NIL utilized a single step patterning approach, process costs are substantially reduced relative to ArF immersion lithography. Overall, NIL currently realizes a 28% cost advantage for this case, but as mask life continues to improve, the cost advantages become much more significant.

Proceedings Article | 26 March 2019 Presentation + Paper

Nanoimprint system alignment and overlay improvement for high volume semiconductor manufacturing

Yukio Takabayashi, Takehiko Iwanaga, Mitsuru Hiura, Hiroshi Morohoshi, Tatsuya Hayashi, Takamitsu Komaki

Proceedings Volume 10958, 109580B (2019) https://doi.org/10.1117/12.2514924

KEYWORDS: Semiconducting wafers, Optical alignment, Wafer testing, Nanoimprint lithography, Distortion, Overlay metrology, Photomasks, Source mask optimization, Optical lithography, Lithography

Read Abstract +

Imprint lithography is an effective and well known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. On test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was demonstrated. SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications. Comparable results were also achieved on device wafers by applying a multi-wavelength alignment strategy and a feed forward strategy to realize align signal convergence within the allocated 0.60 second budget.

Proceedings Article | 19 March 2018 Paper

Performance of a nanoimprint mask replication system

Atsushi Kimura, Kohei Imoto, Chiaki Sato, Kiyohito Yamamoto, Hiroshi Inada, Mitsuru Hiura, Takehiko Iwanaga, Ali Aghili, Makoto Mizuno, Jin Choi, Chris Jones

Proceedings Volume 10584, 105840Q (2018) https://doi.org/10.1117/12.2299636

KEYWORDS: Photomasks, Particles, Semiconducting wafers, Nanoimprint lithography, Optical lithography, Mask cleaning, Lithography, Manufacturing equipment, Capillaries, Ultraviolet radiation

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Proceedings Article | 22 March 2016 Paper

Defectivity and particle reduction for mask life extension, and imprint mask replication for high-volume semiconductor manufacturing

Keiji Emoto, Fumio Sakai, Chiaki Sato, Yukio Takabayashi, Hitoshi Nakano, Tsuneo Takabayashi, Kiyohito Yamamoto, Tadashi Hattori, Mitsuru Hiura, Toshiaki Ando, Yoshio Kawanobe, Hisanobu Azuma, Takehiko Iwanaga, Jin Choi, Ali Aghili, Chris Jones, J. W. Irving, Brian Fletcher, Zhengmao Ye

Proceedings Volume 9777, 97770C (2016) https://doi.org/10.1117/12.2219036

KEYWORDS: Photomasks, Particles, Nanoimprint lithography, Lithography, Semiconductors, Control systems, Semiconductor manufacturing, Ultraviolet radiation, Optical lithography, Dry etching, Semiconducting wafers, Curtains, Liquids, Ceramics, Overlay metrology

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Proceedings Article | 23 October 2015 Paper

Nanoimprint system development and status for high-volume semiconductor manufacturing

Kazunori Iwamoto, Takehiko Iwanaga, S. Sreenivasan, Junji Iwasa

Proceedings Volume 9635, 96350P (2015) https://doi.org/10.1117/12.2197520

KEYWORDS: Photomasks, Particles, Semiconducting wafers, Lithography, Nanoimprint lithography, Overlay metrology, Semiconductors, Semiconductor manufacturing, Control systems, Nanotechnology

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Proceedings Article | 26 March 2007 Paper

Immersion exposure tool for the 45-nm HP mass production

Hiroaki Kubo, Hideo Hata, Fumio Sakai, Nobuyoshi Deguchi, Takehiko Iwanaga, Takeaki Ebihara

Proceedings Volume 6520, 65201X (2007) https://doi.org/10.1117/12.711360

KEYWORDS: Polarization, Semiconducting wafers, Imaging systems, Defect inspection, Refractive index, Overlay metrology, Metrology, Sensors, Optical alignment, Glasses

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