A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.<sup></sup> NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.<sup>-</sup> In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.<sup></sup>Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.
Nanoimprint lithography (NIL) is regarded as one of the candidates for next generation lithography toward singlenanometer manufacturing. Among the wide variety of imprint methods, Jet and Flash Imprint Lithography (J-FIL) process is the most suitable for IC manufacturing for which high productivity and high precision is required. Unlike spin-coating-based NIL process J-FIL process has some capabilities to solve the issue by controlling local resist volume based on pattern design of the patterned mask (template). In order to improve NIL process, in this paper we focus on understanding the occurrence of non-filling defects during resist filling into the template features, and propose the new optimization concept of drop amount and drop arrangement for fast filling and defect reduction.
Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.
Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. Layout and process dependent hotspots become a significant issue for application in smaller pattern size device and, design for manufacturing (DFM) flow comprising imprint process has to be prepared. Focusing on resist drop arrangement method as a process margin expansion knob, simulated non-fill defect is compared with experimental result. Finally, drop arrangement-related hot-spot extraction/modification flow utilizing total NIL simulation is proposed.
Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die-by-die alignment system with moiré fringe detection which gives alignment measurement accuracy of below 1nm. <p> </p>In this paper we describe the evaluation results of NIL the overlay performance using an up-to-date NIL tool for 300mm wafer. We show the progress of both "NIL-to-NIL" and "NIL-to-optical tool" distortion matching techniques. From these analyses based on actual NIL overlay data, we discuss the possibility of NIL overlay evolution to realize an on-product overlay accuracy to 3nm and beyond.
Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. To apply smaller pattern size device, layout dependent hotspots becomes a significant issue, so design for manufacturing (DFM) flow considering imprint process has to be prepared. In this paper, focused on fine resist spread, RLT (Residual Layer Thickness) uniformity improvement utilizing simulation is demonstrated and resist drop compliance check flow is proposed
A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.<sup></sup> NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.<sup>-</sup> In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.<sup></sup> In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm<sup>2</sup> has been achieved at a throughput of 15 wafers per hour.
Since multi patterning with spacer was introduced in NAND flash memory<sup>1</sup>, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.<sup>2, 3</sup> Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL<sup>4, 5, 6</sup>) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.
Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.
A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.
Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is a promising candidate for extremely low-cost fabrication of large-area devices in large volumes. A residual layer thickness (RLT) of a pattern transferred by RtR-NIL distributes at around several micrometers or more. We tried to thin the RLT below 100 nm and confirmed the controllability of the RLT and its deviation in the patterned sample.
Thermal aberration becomes a serious problem in the production of semiconductors for which low-k1 immersion lithography with a strong off-axis illumination, such as dipole setting, is used. The illumination setting localizes energy of the light in the projection lens, bringing about localized temperature rise. The temperature change varies lens refractive index and thus generates aberrations. The phenomenon is called thermal aberration. For realizing manufacturability of fine patterns with high productivity, thermal aberration control is important. Since heating areas in the projection lens are determined by source shape and distribution of diffracted light by a mask, the diffracted pupilgram convolving illumination source shape with diffraction distribution can be calculated using mask layout data for the thermal aberration prediction. Thermal aberration is calculated as a function of accumulated irradiation power. We have evaluated the thermal aberration computational prediction and control technology “Thermal Aberration Optimizer” (ThAO) on a Nikon immersion system. The thermal aberration prediction consists of two steps. The first step is prediction of the diffraction map on the projection pupil. The second step is computing thermal aberration from the diffraction map using a lens thermal model and an aberration correction function. We performed a verification test for ThAO using a mask of 1x-nm memory and strong off-axis illumination. We clarified the current performance of thermal aberration prediction, and also confirmed that the impacts of thermal aberration of NSR-S621D on CD and overlay for our 1x-nm memory pattern are very small. Accurate thermal aberration prediction with ThAO will enable thermal aberration risk-free lithography for semiconductor chip production.
Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning
technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the method's potential for sub-100 nm patterning.
A new overlay control method called "Polar Correction" has been developed.
In the 3x nm half-pitch generation and beyond, even in the case of using a high-end optical exposure system such as
immersion lithography with NA 1.3 over, the overlay accuracy becomes the most critical issue, and the accuracy below
10nm is indispensable . In view of the severe overlay accuracy required, the shot-to-shot intra-field overlay control
cannot be disregarded in this generation. In particular, the shot-to-shot intra-field overlay error caused by the influence of
evaporation heat has been added in the immersion exposure system. However, it is impossible to correct the shot-to-shot
intra-field overlay error by the conventional overlay control method. Therefore, we have developed the new overlay
control method called Polar Correction for higher-order intra-field error dependent on the wafer coordinates.
In this paper, we explain our new overlay control method for higher-order intra-field error, and show the simulation data
and the experimental data. We believe that Polar Correction corresponds to the generation below 10nm overlay
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
Mask specifications of the pitch splitting type double patterning for 22nm node and beyond in logic
devices have been discussed. The influences of the mask CD error and the mask induced overlay
error on wafer CD have been investigated in both cases of bright field and dark filed. The
specification for intra-layer overlay alignment is much smaller than inter-layer one. The specification
of mask CD uniformity for dark is more challenging. In order to overcome the technology gap
between single patterning and double patterning, many things will have to be improved.
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um<sup>2</sup> area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
This paper proposes a new virtual lithography system to improve the productivity of high-mix / low-volume production. In the case of the conventional technique, product mask and wafer are used to determine a focus-exposure-matrix (FEM) exposure condition.
The conventional technique is a "send-ahead" process involving exposure, metrology and data analysis that decreases productivity of manufacturing. In the case of low-volume/high-mix ASIC manufacturing, such a send-ahead process is particularly time-consuming and costly. Moreover, the exposure condition setting imposes a huge workload that is desirable to be avoided from the viewpoints of cost and TAT. Thus, a new methodology to determine exposure dose conditions for each mask in high-mix / low-volume production is required.
In this paper, we propose a virtual lithography system to eliminate send-ahead exposure. Firstly, to improve wafer CD prediction accuracy, we rebuild the system, thereby transforming it from a training-based system to a simulation-based system. To make simulation models, we use a golden mask, which is not a product mask. Secondly, exposure conditions are determined by considering 2D patterns including hotspot patterns. Thirdly, the lithography simulation is carried out for each exposure tool. Using the golden mask, we calibrate simulation models for each exposure tool<sup>1-3</sup>. Various patterns including hotspots likely to become fatal errors for circuit reliability due to process proximity effects are considered. The virtual system provides optimal exposure parameters according to product and layer, considering long-term variation of exposure tool conditions. By developing this system, TAT and cost for the determination of exposure parameters will be improved. Elimination of send-ahead wafers can reduce TAT from mask delivery to exposure condition setup in high-mix / low-volume production. Drastic cost reduction is realized in high-mix / low-volume production.
In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained
on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor
was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities.
The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than
11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design.
The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability
values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including
flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The
jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer
alignment performance. On-product overlay results on manufacturing wafers were measured for three different process
layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer
alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor.
Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for
the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as
determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By
applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending
on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution
for wafers containing a semi-transparent hard-mask layer.
Immersion lithography with ArF light and Ultra Pure Water (UPW) is the most promising technology for semiconductor manufacturing with 65 nm hp design and below. Since Nikon completed the first full-field immersion scanner, the Engineering Evaluation Tool (EET, NA=0.85) at the end of 2004, Toshiba and Nikon have investigated overlay accuracy with the EET which uses the local fill nozzle. EET successfully demonstrated immersion tools are comparable in single machine overlay accuracy to dry tools, and immersion-dry matching has the same level overlay matching accuracy as dry-dry matching. EET also made it clear that overlay accuracy is independent of scanning speed, and both solvent-soluble topcoats, as well as developer-soluble topcoats can be used without degradation of overlay accuracy. We investigated the impact of the thermal environment on overlay accuracy also, assuming that a key technology of overlay with immersion tools must achieve thermal stabilities similar to dry tools. It was found that the temperature of supply water and loading wafer are stable enough to keep the overlay accuracy good. As for evaporation heat, water droplets on the backside of the wafer lead to overlay degradation. We have decided to equip the wafer holder of S609B, the first immersion production model, with an advanced watertight structure.
Recently, requirements concerning overlay accuracy have become much more restrictive. For the accurate overlay, signal intensity and wave form from the topographical alignment mark have been examined by signal simulation. However, even if the results were in good agreement with actual signal profiles, it would be difficult to select particular alignment marks at each mask level by the signal simulation. Therefore, many mark candidates are left in the kerf area after mass production. To facilitate the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation performed in advance. In our system, the alignment mark signal can be easily simulated after input of some process material parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. Imaging of the reflected beams through inspection optics is simulated. In addition, we show two applications. This system is not only for predicting and showing a signal wave form, but is also helpful for finding the optimum marks.
Recently the overlay accuracy has got seriously severe. For the accurate overlay, signal intensity and waveform from the topographical alignment mark has been examined by signal simulation. Actually these results have given good agreements with actual signal profiles, but it is difficult to select particular alignment marks in each mask level by the signal simulation. Even after mass production, many mark candidates leave in kerf area. To help the selection, we propose a mark TCAD system. It is a useful system for the mark selection with the signal simulation in advance. In our system, alignment mark signal can be very easily simulated after input of some process parameters and process of record (POR). The POR is read into the system and a process simulator makes stacked films on a wafer. Topographical marks are simulated from the stacked films and the resist pattern. The topographical marks are illuminated and reflected beams are produced. It is simulated how the reflected beams are imaged through inspection optics. We show two applications. This system is not only to predict and show a signal waveform, but also helpful to find optimum marks.
This paper discusses the compensation method and APC system to reduce errors in mix and matching overlay between scanners. We proposed the compensation model for intra-field errors in mix and matching. And we developed the advanced APC system also to improve dynamic scan distortion using the compensation model.