The intention of this study is to develop an immersion lithography process using advanced track solutions to achieve
world class critical dimension (CD) and defectivity performance in a state of the art manufacturing facility. This study
looks at three important topics for immersion lithography: defectivity, CD control, and wafer backside contamination.
The topic of defectivity is addressed through optimization of coat, develop, and rinse processes as well as
implementation of soak steps and bevel cleaning as part of a comprehensive defect solution. Develop and rinse
processing techniques are especially important in the effort to achieve a zero defect solution. Improved CD control is
achieved using a biased hot plate (BHP) equipped with an electrostatic chuck. This electrostatic chuck BHP (eBHP) is
not only able to operate at a very uniform temperature, but it also allows the user to bias the post exposure bake (PEB)
temperature profile to compensate for systematic within-wafer (WiW) CD non-uniformities. Optimized CD results, pre
and post etch, are presented for production wafers. Wafer backside particles can cause focus spots on an individual
wafer or migrate to the exposure tool's wafer stage and cause problems for a multitude of wafers. A basic evaluation of
the cleaning efficiency of a backside scrubber unit located on the track was performed as a precursor to a future study
examining the impact of wafer backside condition on scanner focus errors as well as defectivity in an immersion
Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns,
we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic
patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow
angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is
used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For
2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist
pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular
illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns,
it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination
of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.
We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the
28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask
topography effect and the oblique-incidence. Using the rigorous lithography simulation considering
the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum
pitch required in 28nm node. The optimum mask plate and illumination conditions have been
decided by simulation. The experimental results for 28nm node show that the minimum pitch
patterns and minimum SRAM cell are clearly resolved by single exposure.
We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.
We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure
conditions. The simulation and experimental results indicate that the minimum pitches should be
determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated
feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly
resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability.
There is no immersion induced defects.
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity
control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node
advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from
our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the
critical layers according to the substrate transparency. Another key issue in terms of material process was described in
this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without
any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA
immersion lithography and pattern transfer performance using single BARC
Immersion lithography was applied to 45nm node logic and 0.25um2 ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lithography enabled to apply the attenuating phase shift mask to the gate level. The enough lithography margin for the alternating phase shift mask was also obtained by using not only immersion tool but also dry tool for gate level. The immersion lithography shrunk the minimum hole pitch from 160nm to 140nm. Thus, the design rule for 45nm node became available by using immersion lithography.