Extreme ultraviolet lithography is one of the promising high volume manufacturing processes for devices below 7 nm node and beyond. However, resist pattern collapse is one of the hurdles in achieving a comfortable process margin/window for resist patterning. To suppress this resist pattern collapse and to improve manufacturing process margin, undoubtedly it is a well-known fact that the rinse materials can mitigate a pattern collapse at development process.
In this study, we focus on the relationship between resist swelling and pattern collapse, based on the assumption of resist pattern softening induced by resist swelling and further resist pattern bending or deformation which could be classified as pattern collapse. To verify this model, two samples of Rinse-A and Rinse-B which showed similar capillary force but different resist swelling behavior expected, respectively, were prepared. And the hardness of the resist films treated using those rinse materials together with de-ionized water as reference rinse, were measured using nano-indentation measurement technique.
From the result, it was found that Rinse-A had the resist film hardness reduced by 7.9 % as compared to that on de-ionized water. On the other hand, Rinse-B which was designed to suppress the penetration of additives into the resist film, exhibited comparable hardness property to that on reference rinse, de-ionized water. Finally, the evaluation of lithographic performance of the photoresist in different rinse process conditions using Rinse-A and Rinse-B was carried out, and Rinse- B achieved 12.7 nm minimum pattern size of resist feature at 16 nm half pitch printing by interference projection system on Extreme Ultraviolet lithography, whereas Rinse-A showed 16.5 nm.
In this paper, we will discuss the improvement of resist pattern roughness on NTD (Negative Tone Development) resist by chemical shrink process. Chemical shrink process is one of the most practical approaches to achieve small feature size CH (Contact Hole) or trench with ArF immersion lithography. We found that this shrink material has not only general benefits of shrink process like DOF (Depth of Focus) margin improvement, but also demonstrates a pattern smoothing effect through observation of the surface of shrink layer using SPM (Scanning Probe Microscope). Additionally, an improvement of LWR (Line Width Roughness) over 16% and an improvement of LCDU (Local Critical Dimension Uniformity) around 60% were observed.
Negative tone shrink materials (NSM) suitable for resolution enhancement of negative tone development (NTD) 193nm immersion resists have been developed. While this technology is being expanded to integrated circuits (IC) manufacturing, there still have two major problems to apply various processes. One of them is shrink ID bias which means shrink differences between isolated (I) and dense (D) CDs, and the other one is Y/X shrinkage bias which means shrinkage differences between major axis (Y) and minor axis (X) of the elongated or oval shape pattern. While we have presented the improvement of shrink ID bias at SPIE2014 , the reduction of Y/X shrinkage bias was the examination theme for quite some time. In this paper, we present Y/X shrinkage bias of current NTD shrink material, new concept material for Y/X bias reduction and the result of new shrink material. Current NTD shrink model has Y/X bias of 1.6 (Y shrink=16nm) at a mixing bake (MB) of 150°C on AZ AX2110P NTD elongated pattern of X=70nm and Y=210nm ADI. This means shrinkage of Y has larger shrinkage than X and that makes difficult to apply shrink material. We expected that the characteristic shape of elongated pattern was one of the root-cause for Y/X bias, and then simulated how to achieve equivalent shrinkage at Y and X. We concluded that available resist volume per each Y and X unit was not equivalent and need new shrink concept to solve Y/X bias. Based on our new concept, we prepared new shrink material which has lower Y/X bias and larger shrink amount compared with current NTD shrink material. Finally we have achieved lower Y/X bias from 1.6 to 1.1 at MB150°C and moreover got higher shrinkage than current NTD shrink material from 10.1nm to 16.7nm.
In this paper, we discuss a new approach to improve the resist roughness, which is applied after the lithography process. The ERC (Edge Roughness Controller) process is composed of two steps, 1) To deliver resist softening material at the resist surface 2) To give thermal flow at that region in the bake step. Several samples were prepared based on this concept and consistent improvement was observed. Finally, by optimizing ERC chemistry using HSP (Hansen Solubility Parameter), LWR improvement of 14.8% could be achieved.
Negative tone shrink materials (NSM) suitable for resolution enhancement of negative tone development (NTD) 193nm immersion resists have been developed. While this technology is being applied to integrated circuits (IC) manufacturing, reduction of shrink differences between isolated and dense (ID) CDs also called as shrink ID bias is the challenge to meet wide-spread applications. In this paper, we present the effects of resist thermal flow, proximity effects of DUV exposure, flood exposure of after developed image (ADI) on the NSM shrink. High mixing bake (MB) temperature (example 170°C) during the shrink process resulted in increased resist thermal flow leading to worse shrink ID bias of 3.5 nm. As different pitch pattern has different proximity effect and matching with illumination condition, uneven dose is expected on them. These differences in dose required to obtain same through pitch (1:X, X-1, 1.5, 2, 3, 5) CD was assigned as the cause for shrink ID bias as the de-protection chemistry is related to dose which affects the shrink amount. This was further confirmed by flood exposure of after developed image (ADI) which reduced shrink ID bias from 3.5 nm to 1.8 nm. We concluded that the flood exposure makes the ADIs of the resist chemically uniform thereby minimizing shrink ID bias. Based on these studies, a mechanism for shrink ID bias is proposed. A modified NSM with 1.2 nm shrink ID bias has been developed without the need for the flood exposure.
The negative tone development (NTD) process has proven benefits for superior imaging performance in 193nm
lithography. Shrink materials, such as AZ® RELACS® have found widespread use as a resolution enhancement
technology in conventional 248nm (DUV), 193 nm dry (ArF) and 193 nm immersion (ArFi) lithography. Surfactant
rinses, such as AZ® FIRM® are employed as yield enhancement materials to improve the lithographic performance by
avoiding pattern collapse, eliminating defects, and improving CDU. This paper describes the development and recent
achievements obtained with new shrink and rinse materials for application in NTD patterning processes.
A phase segregating polymer blend comprising a SOD precursor polysilazane and an organic polymer PSαMS
[poly(styrene-co-α-methyl styrene)] was studied. By utilizing similar approaches employed in DSA (directed
self-assembly) such as patterned substrates, surface chemical modification etc and their combination, we achieved 2xnm
spacer and airgap-like structure. Vertical phase separation and cylinder microdomains in the film of this blend can be
straightforwardly observed by cross-section SEM (Scanning Electron Microscope) respectively. The airgap-like structure
derived from cylinder microdomains was directly obtained on ArF resist pattern. Spacer derived from vertical phase
separation was obtained on pretreated ArF resist pattern.
Patternable dielectric materials were developed and introduced to reduce semiconductor manufacturing complexity and
cost of ownership (CoO). However, the bestowed dual functionalities of photo-imageable spin-on dielectrics (PSOD)
put great challenges on the material design and development. In this work, we investigated the combinatorial process
optimization for the negative-tone PSOD lithography by employing the Temperature Gradient Plate (TGP) technique
which significantly reduced the numbers of wafers processed and minimized the developmental time. We demonstrated
that this TGP combinatorial is very efficient at evaluating the effects and interactions of several independent variables
such as post-apply bake (PAB) and post-exposure bake (PEB). Unlike most of the conventional photoresists, PAB
turned out to have a great effect on the PSOD pattern profiles. Based on our extensive investigation, we observed great
correlation between PAB and PEB processes. In this paper, we will discuss the variation of pattern profiles as a matrix
of PAB and PEB and propose two possible cross-linking mechanisms for the PSOD materials to explain the unusual
From the perspectives of IC fabrication simplification, cost reduction, and waste material cutback, it is highly desirable
to combine the traditional pattern formation step (lithographical processes) and the pattern transfer step (etch processes)
into a single step. Photo-imageable spin-on dielectrics (PSOD) render it possible to achieve the aforementioned goal.
However, the bestowed dual functionalities on PSOD put great challenges on the material design and development.
PSOD needs not only to match all the performances of the advanced resists, but also to undertake all the duties of the
dielectrics on the chips. We wish to report our modular approach employing Si-containing materials to address the
challenge and to meet the requirements from the different material roles. This paper will also discuss the investigation
and progress on lithographic performance, cure behaviors, thermal stability, and electrical and mechanical properties.
Conventional trilayer schemes alleviate the decreasing photoresist budgets as well as satisfy the antireflection issues
associated with high NA imaging. However, a number of challenges still exist with standard trilayer processing, most
notable among which is the lack of broad resist compatibility and trade-offs associated with improving Si content, such
as stability and lithography performance. One way to circumvent these issues is to use a silicon hard mask coated over a
photoresist image of reverse tone to the desired pattern. Feasibility of this image reversal trilayer process was
demonstrated by patterning of trenches and contact holes in a carbon hard mask from line and pillar photoresist images,
respectively. This paper describes the lithography, pattern transfer process and materials developed for the image
reversal trilayer processing.