Imaging page-oriented optical data storage, with its high bit packing density and many parallel readout channels, offers a solution for high capacity data storage with fast data transfer rate. As in any data storage system, increasing the packing density increases the effect of inter-symbol interference (ISI) and inter-page interference (IPI). We describe a combination of modulation encoding/decoding and error correction that overcomes this interference allowing high packing density in the presence of noise while maintaining acceptable bit error rate (BER). We also describe an extension of the algorithm to multi-level (grayscale) encoding.
We propose a new method to determine dynamically the threshold in volumetric (3D) page-oriented optical data storage (PODS) systems that use an incoherent (non-holographic) imaging format. In these systems, the inter-symbol interference (ISI) and inter-page interference (IPI) that occurs with very high data packing density are two major sources of error during data retrieval. Traditional readout systems based on a fixed binary decision threshold provide poor results. Our variable threshold detection method identifies the amount of interference from three dimensions for each data element (pixel) and adjusts the threshold value based on that information. In simulation results, the variable threshold method exhibits significant improvement over traditional detection methods.
We describe equalization and detection techniques that overcome both inter-page interference (IPI) and intersymbol interference (ISI) in volumetric (3D) page-oriented optical data storage (PODS) systems.
We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.