The reduction of line width roughness (LWR) is a critical issue in developing resist materials for EUV lithography and
LWR represents a trade-off between sensitivity and resolution. Additional post pattern processing is expected as an LWR
reduction technique without impact to resolution or sensitivity. This paper reports the LWR reducing effect of a post-development
resist-smoothing process. Approximately 20% improvement in LWR for ArF immersion exposed resist patterns was achieved for two types of resist and two illumination conditions. The LWR after BARC etching in which
resist-smoothing was applied was decreased relative to the case in which smoothing was not applied. Resist-smoothing
process also reduced LWR of an EUV exposure resist pattern by approximately 10%. These results confirm that resistsmoothing
process is robust for different resists and illumination conditions.
In the field of photolithography, a variety of resolution enhancement techniques (RETs) are being applied under the mainstream technology of 193-mm water-based immersion lithography. The resolution performance of photoresist, however, is limited at 40 nm. Double patterning (DP) is considered to be an effective technology for overcoming this limiting resolution. Many double-patterning techniques have come to be researched such as litho-etch-litho-etch (LELE), litho-litho-etch (LLE), and self-aligned spacer DP, but as the pattern-splitting type of double patterning requires high overlay accuracy in exposure equipment, the self-aligned type of double patterning has become the main approach. This paper introduces the research results of various double-patterning techniques toward 22nm nodes and touches upon newly developed elemental technologies for double patterning.
Exposure wave length has been changing rapidly with the shrink of design rule. In 32nm node and beyond, it is predicted
that keeping good resolution performance of resist pattern with small dimension and high density will be more difficult
due to the drop of optical contrast in 193nm immersion lithography. EUV lithography and Double Patterning using
193nm immersion lithography are being investigated as alternative technologies, but it is currently difficult to keep
enough process margins in device fabrication. Resist slimming technology by dry process and exposure process is also
being investigated based on these technical backgrounds but many technical challenges have been reported. We started to
develop our original resist slimming technology in track process with the aim of overcoming technical challenges and
cost reduction, which is one of main challenges in double pattering. In this paper, we report the basic characteristics of
our resist slimming process (controllability of CD shrink, CD uniformity within wafer, LWR, and total process margin)
and also pattern transfer performance of CD and LWR after dry etching in order to apply this slimming technology to
As part of the trend toward finer semiconductor design rules, studies have begun in the field of semiconductor
lithography technology toward the 32nm-node and 22nm-node generations. The development of various types of
fine-processing technologies is underway and particular progress is being made in the development of high numerical
aperture (NA) technology and extreme ultraviolet (EUV) lithography for 32nm processes and beyond. At present,
however, many technical issues are still being reported. One problem of special concern relates to the forming of fine,
high-density trench patterns. Here, the required process margin is difficult to achieve by existing fine-processing
techniques compared to lines and space patterns, and it is predicted that this problem could be a factor in lower yields
caused by pattern defects. To solve this problem, studies have begun on double patterning technology and various shrink
technologies. To place the joint use of these technologies on the road toward genuine mass-production applications, it is
becoming increasingly important that comprehensive efforts be made to improving the basic performance of
exposure-equipment and single lithography processes, to improving the alignment accuracy in double patterning, and to
extract problem points in critical-dimension (CD) and defect control toward an exposure-equipment/ coater/developer
cluster tool. In the face of these technical issues, NIKON Corporation and Tokyo Electron Ltd.(TEL) have joined forces
to study technology for forming fine, high-density trench patterns and have successfully developed a fine, high-density
trench-pattern formation process through the joint use of double patterning technology and original Chemical Vapor
Deposition (CVD)-shrink technology. This paper reports on the results of a comprehensive process evaluation of double
patterning technology using lithography clusters, CVD tools and etching tools.
It is supposed that double patterning process is one of the promising candidates for making mask pattern for dry etching
at 32nm and 22nm node. Currently, drastic improvement of overlay of scanner is considered to be the most important
challenge and much attention has been paid to sidewall spacer process since it can avoid that problem and also can
provide easier method to fabricate patterns repeatedly. In this paper, material option of core pattern, spacer pattern and
hard mask, which are main components of this process, is presented and 32nm gate pattern is actually fabricated after
process optimization. In addition, line-width-roughness (LWR), whose reduction is becoming more and more necessary,
is measured in each process step of spacer process.
Exposure wavelength has been changing dramatically as semiconductor design rules shrink, and for 32nm-node fine processes and beyond, it is predicted that the drop in optical contrast when using 193nm immersion lithography exposure technology will make it difficult to ensure good resolution performance in fine and dense resist patterns. To address this problem, studies have begun on extreme ultraviolet (EUV) lithography technology and double patterning technology that uses 193nm immersion lithography as alternative technologies, but many problems have been reported at the present stage of development.
Against the above background, we investigated various process flows with the aim of reducing production processes and cost in double patterning technology that uses 193nm immersion lithography. We consequently developed an advanced process technique for use after 1st resist pattern formation and established a litho-litho-etch (LLE) process. The application of this technology decreases the number of total processes used in ordinary double patterning technology.
In this paper, we focus on double patterning technology in 193nm immersion lithography and report on the performance of our original advanced process technique and on our evaluation of double patterning technology.
Line width roughness (LWR) reduction is a critical issue for low k1 ArF immersion lithography. Various approaches
such as materials, exposure technology and the track process have been performed for LWR reduction during
It was reported that the post-development bake process had good performance for LWR reduction (1). However, the
post-development bake process induced large CD change owing to the degradation of large isolated resist pattern.
Therefore post-development process with small iso-dense bias is required in low k1 ArF immersion lithography.
The resist smoothing process is one of the candidates for LWR reduction with small iso-dense bias. This method
whereby the resist pattern surface is partially melted in organic-solvent atmosphere was shown to have a significant
LWR reduction effect on resist patterns. This paper reports on the application of the resist smoothing process to the
ArF immersion resist pattern after development. It was found that the resist smoothing process was effective to reduce
LWR for ArF immersion resist. As a result of LWR trace from after development to after the hard mask etching process,
the effect of LWR reduction with the resist smoothing process continued after the hard mask etching process.
Furthermore CD change of large isolated patterns with the smoothing process was smaller than in the case of post-development
bake process. We confirmed that the resist smoothing process is an effective method for decreasing LWR
in ArF immersion lithography.
As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues.
In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.
With 32nm and 22nm feature size node in the near future, Double patterning type processing will be in
mainstream device manufacturing in most cutting edge Fabrication facilities. These type of processes
requires cooperation between the litho cell and the other processing modules. In a collaboration
between ASML and TEL we have developed a integrated solution to image 30nm Contacts. We
describe a novel technique to achieve a geometric shrink from a starting geometry of 65nm down to the
final feature size of 30nm for each of the two contact images Processing 2 images separately could
produce two distinct populations for alignment and critical dimensions. We will show the ability to
image 65nm contacts on a 130nm pitch with acceptable process windows and then apply the novel CD
shrink process to shrink the 65nm contacts to 30nm final dimension. The second level of contacts is
imaged in between the 1st set of contacts allowing us to image a 32nm ½ pitch contact pattern.
We show the ability to Image 2 separate sets of contacts using a split clip layout with a single
distribution for critical output parameters. We address the following process challenges:
1) Overlay capability across the slit and across the field.
2) Critical Dimension capability across the slit and across the Field.
3) Sidewall angle integrity with acceptable process window.
Using the novel CD shrink process TEL has developed and imaging capability of the an ASML 1700i
TWINSCAN, we can achieve a double pattern contact process with acceptable process capability.
For the scaling down of the semiconductor design rule, 193-nm lithography technology is entering the 65-nm-node
generation. In 65-nm and finer processes, the practical application of 193-nm immersion lithography is progressing due
to its high numerical aperture (NA), which is achieved by using de-ionized water (DIW) as the medium between the lens
and wafer in the exposure system. Immersion lithography, however, generates two main concerns: the penetration of
moisture into resist film and the leaching of resist components into DIW as a result of immersing the resist film in DIW.
To prevent these effects, the use of a topcoat process has been adopted, but there have been reports that defects caused
by remaining droplets on the topcoat or particles can be transferred to the resist pattern and degrade resolution. Research
to date has clarified the generation mechanism of defects due to water droplets, and the importance of preventing
droplets from remaining is now understood. However, there are few research reports on the generation of particles, and
to reduce defects caused by the immersion process. It is essential that the generation mechanism of particle-related
defects on the resist pattern be clarified and that a suitable approach to reducing particles is needed. It is also known that
particles on the resist pattern that acts as a mask in the dry etching process can be associated with defects in etching,
which makes particle control in the process steps between lithography and dry etching all the more important.
In this paper, we clarify the defect-generation mechanism on resist pattern due to particles put on
topcoat and investigate the effects of such particles on the dry etching process.
Immersion lithography is widely expected to meet the manufacturing requirements of future device nodes. A critical
development in immersion lithography has been the construction of a defect-free process. Two years ago, the authors
evaluated the impact of water droplets made experimentally on exposed resist films and /or topcoat. (1) The results
showed that the marks of drying water droplet called watermarks became pattern defects with T-top profile.
In the case that water droplets were removed by drying them, formation of the defects was prevented. Post-exposure
rinse process to remove water droplets also prevented formation of the defects.
In the present work, the authors evaluated the effect of pre- and post-exposure rinse processes on hp 55nm line and
space pattern with Spin Rinse Process Station (SRS) and Post Immersion Rinse Process Station (PIR) modules on an inline
lithography cluster with the Tokyo Electron Ltd. CLEAN TRACKTM LITHIUS TM i+ and ASML TWINSCAN
XT:1700Fi , 193nm immersion scanner.
It was found that total defectivity is decreased by pre- and post-exposure rinse. In particular, bridge defects and large
bridge defects were decreased by pre- and post-exposure rinse.
Pre- and post-exposure rinse processes are very effective to reduce the bridge and large bridge defects of immersion
With the scaling down of the semiconductor design rule, the requirement to reduce the roughness of the resist pattern used in lithography processing has become crucial. Two typical examples of resist-pattern roughness are line-edge roughness (LER) and line-width roughness (LWR). In particular, as the wavelength of the optical light source has been shortened from 248 nm (KrF source) to 193 nm (ArF source), the problem that LWR is produced with a scaled-down ArF resist pattern has become a cause of deterioration in device characteristics. And with further scaling down in the future, decreasing this LWR on the resist pattern will become a major challenge facing lithography processing. Accordingly, to meet this challenge, it has thus become urgent to find a good method for reducing LWR. At present, for LWR reduction during lithography processing, various measures have been tried and many studies taking different approaches-addressing materials (resist, etc.), exposure technology (mask, etc.), and the track process-have been performed. A decisive method of reducing LWR, however, has not yet been found. Aiming at reducing LWR, we have thus developed a process for treating the post-development resist pattern in an organic-solvent atmosphere. This resist smoothing process is effective method for both Krf resist and Arf resist, moreover it was achieved that VUV pre-treatment improve solvent solubility against resist, especially Arf resist. As a result, the LWR of a resist pattern after undergoing this treatment process was substantially decreased. Moreover, as for the roughness produced during the following etching process for forming the gate electrode, it was confirmed that the effect of decreasing LWR of the resist pattern is carried forward to this next process. In this paper, the developed LWR-reduction method for an ArF ultra-fine pattern is explained, and LWR reduction results achieved with method are presented.
Utilizing de-ionized water as the medium between the wafer and lens of the exposure system and realizing high numerical aperture (NA), 193-nm immersion lithography is being developed at a great pace towards practical application. Recent improvements in materials, processing and exposure systems have dramatically reduced the defectivity levels in immersion processing. However, in order to completely eradicate immersion related defects and achieve defectivity levels required for ideal productivity, further investigation into the defect generation mechanism and full understanding of the improvements garnered so far is required. It is known that leaching of resist component materials during exposure and penetration of remaining water from the immersion scanning process are two key contributors towards immersion related defects. Additionally, the necessity to increase the hydrophobicity of the resist materials has had a signification effect on remaining resist residues. In order to more fully understand the generation of defects from the these contributions, it is necessary not only to analyze properties of the defects, but also investigate the change in composition originating from advanced processing techniques that have shown improvements in defectivity performance.
For immersion lithography at 193 nm, there is concern that the immersion of resist in water during exposure might cause water to penetrate the resist or resist components to dissolve into water, or that water remaining after exposure might affect subsequent processes. It is also thought that the same concerns are likely to be felt even if using a protective top coat. In this paper, we report on three key findings. First, after immersing resist in water using virtual immersion methods and evaluating the effect of water on critical dimension (CD) and defects, it was found that CD changes and defects increase. Second, as a result of performing the same evaluation when using a top coat, it was found that CD changes and defects increase despite top-coat application. Finally, a significant amount of knowledge can be obtained for the development of optimal 193-nm immersion lithography equipment as a result of wafer processing using real inline tools for immersion exposure and coating/developing.
In the liquid immersion lithography, uses of the cover material (C/M) films were discussed to reduce elution of resist components to fluid. With fluctuation of exposure tool or resist process, it is possible to remain of waterdrop on the wafer and watermark (W/M) will be made. The investigation of influence of the W/M on resist patterns, formation process of W/M, and reduction of pattern defect due to W/M will be discussed. Resist patterns within and around the intentionally made W/M were observed in three cases, which were without C/M, TOK TSP-3A and alkali-soluble C/M. In all C/M cases, pattern defect were T-topped shapes. Reduction of pattern defects due to waterdrop was examined. It was found that remained waterdrop made defect. It should be required to remove waterdrop before drying, and/or to remove the defect due to waterdrop. But new dry technique and/or unit will be need for making no W/M. It was examined that the observation of waterdrop through the drying step and simulative reproduction of experiment in order to understand the formation mechanism of W/M. If maximum drying time of waterdrop using immersion exposure tool is estimated 90 seconds, the watermark of which volume and diameter are less than 0.02 uL and 350um will be dried and will make pattern defect. The threshold will be large with wafer speed become faster. From result and speculations in this work, it is considered that it will be difficult to development C/M as single film, which makes no pattern defects due to remained waterdrop.
As feature sizes become increasingly smaller in integrated circuits, the occurrence of resist-pattern defects (resist poisoning) has become a serious problem in Back End Of Line (BEOL) Dual Damascene (DD) processing. Against this background, we have researched a bi-layer silylation process as one type of multi-layer process and evaluated its effectiveness as a countermeasure to resist poisoning. In the bi-layer silylation process, two layers of chemically amplified resist (CAR) are formed on novolac, and after wet-developing the upper CAR layer by an alkali developer, a silylation reaction is generated to make the resist pattern resistant to O2 reactive ion etching (RIE). We found that the bi-layer silylation process was an effective countermeasure to resist poisoning in a methylsilsesquioxane (MSQ) DD structure with a 160-nm via, and that a 160-nm MSQ DD structure could be formed. We also found that the occurrence of resist poisoning depended greatly on the surface conditions of the via structure and on the resist-ashing technique.