ArF immersion lithography has been introduced in mass production of 55nm node devices and beyond as the post ArF
dry lithography. Due to the existence of water between the resist film and lens, we have many concerns such as leaching
of PAG and quencher from resist film into immersion water, resist film swelling by water, keeping water in the
immersion hood to avoid water droplets coming in contact with the wafer, and so on. We have applied to the ArF dry
resist process an immersion topcoat (TC) process in order to ensure the hydrophobic property as well as one for
protecting the surface. We investigate the TC-less resist process with an aim to improve CoO, the yield and productivity
in mass production of immersion lithography.
In this paper, we will report TC-less resist process development for the contact layer of 40nm node logic devices. It is
important to control the resist surface condition to reduce pattern defects, in particular in the case of the contact layer.
We evaluated defectivity and lithography performance of TC-less resist with changing hydrophobicity before and after
development. Hydrophobicity of TC-less resist was controlled by changing additives with TC functions introduced into
conventional ArF dry resist. However, the hydrophobicity control was not sufficient to reduce the number of Blob
defects compared with the TC process. Therefore, we introduced Advanced Defect Reduction (ADR) rinse, which
was a new developer rinse technique that is effective against hydrophobic surfaces. We have realized Blob defect
reduction by hydrophobicity control and ADR rinse. Furthermore, we will report device performance, yield, and immersion defect data at 40nm node logic devices with TC-less resist process.
In addition to being more accurate and non-destructive compared to CD-SEM metrology, scatterometry provides more information that is usable for Advanced Process Control (APC). The integrated Optical Digital Profilometry (iODP) scatterometry tool included in the TEL Clean Track product line is designed to give not only a quick in-line pattern characterization but also to allow possible identification and correction of the parameters responsible for the process variation. In the case of a trapezoidal approximation of the resist profile, three partially independent responses such as top CD, sidewall angle and height of the pattern are available. If the process drifts, it is likely that the pattern shape will behave differently depending on the parameter responsible for the variation. A design of experiment was run on a 100nm process with different resist softbake (PAB), exposure, focus and post-exposure bake (PEB) conditions. The data measured by iODP was then analyzed using a multivariate technique. A Projection to Latent Structures (PLS) model was built between the processing conditions and the profile measurement enabling the separation of three groups of profile variation. Additional experiments have shown that variations of bottom antireflective thickness can be separated from the other process parameters.