PROCEEDINGS ARTICLE | May 4, 2005
Proc. SPIE. 5753, Advances in Resist Technology and Processing XXII
KEYWORDS: Lithography, Etching, Polymers, Copper, Dielectrics, Silicon, Coating, Reflectivity, Photoresist materials, Semiconducting wafers
In the case of LSI pattern rules with linewidth of 0.1μm or less, the conventional LSI process is no longer adequate and new process and materials are needed to further enhance the performance of LSI. The materials used to reduce delay include a wiring material, Cu, and a low-k film for interlayer insulation. The technology specially developed for using Cu instead of Al as a wiring material is Dual Damascene process (DD process). In DD process, bottom anti-reflective coating (BARC) and gap fill materials are applied on a substrate of huge topography. Therefore, the gap fill material has to provide a coating of reduced thickness bias between the areas of isolated-via and dense-via, have a higher etch rate than ArF resists, be void free, and have no intermixing with resists and BARC.
In order to achieve lower dielectric constant, porous low-k materials will be used at BEOL for the next generation. Etch rates of porous low-k materials are higher than that of conventional low-k materials, which in turn requires a gap fill material of even higher etch rate. This paper describes the new BARC and gap fill material with high etch rate for 45 - 65 node DD processes. The polymer of new materials applies high oxygen content for high etch rate. The performance and via-filling properties in BARC (NCA4401C) and gap fill material (NCA2131) are discussed.
