Proc. SPIE. 10962, Design-Process-Technology Co-optimization for Manufacturability XIII
KEYWORDS: Transceivers, Extremely high frequency, Metals, Manufacturing, Design for manufacturing, Analog electronics, Digital electronics, Yield improvement, Chemical mechanical planarization, Design for manufacturability
A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements.
In this paper, we describe an integrated design space analysis approach consisting of full factorial layout
generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo
simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick
turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable
design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and
cell boundary situations, which are critical for a place and routed block. These interconnects developed using the
integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T
libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.