Existing approaches to predict those locations in a full-chip layout representing a high risk of structural failure, i.e.,
bridging or pinching, either rely on lithography simulation using empirical resist models or on a more abstract empirical
analysis of aerial image characteristics. Both approaches bear the risk of extrapolating an empirical model well beyond
the regime within which it was calibrated and where it can be considered reliable. In this paper, we present as an
alternative a systematic method (a) to build a simple, sturdy "constant threshold" (CTR) model that is valid over the
required process window and (b) to determine empirical criteria for structural failure detection based on simulations
with this CTR model. Even though such a model is not capable of accurately predicting the dimension of structures, it
captures trends of the printing behavior very well, even into the failure regime. From standard wafer data, such as used
for "optical proximity correction" (OPC) model building, it is straightforward to find out which test structures are not
resolved well with a given process. Combined with the CTR model simulation results, this can be used to determine
threshold values for the space and width of simulated structures that indicate structural failure, separately for bridging
and pinching. The predictive power of this approach has already been verified on hardware and is used in production.
"Sub-resolution assist features" (SRAFs) are a standard "resolution enhancement technique" (RET) to ensure the lithography process window of narrow lines for critical mask levels. Since placement rules for SRAFs commonly demand a fixed, constant separation from the edges of the main features to be assisted, small jogs and notches in the layout of the main features force an SRAF interruption. As a consequence, locally the process window is reduced. In addition, jogs and notches increase the data amount and may cause an increase of run time of "design rule check" (DRC), "optical proximity correction" (OPC), and "mask data preparation" (MDP). In most cases, these jogs and notches are completely unnecessary for the electrical functionality of the circuit and the design rule compliance of the layout. In order to detect such superfluous layout features and give the physical designer the opportunity to remove them, a new approach to design rule checking was developed. This approach is based on the decomposition of the layout of one mask level into its basic geometrical features (e.g., corners, line ends, junctions) and a subsequent classification of these features according to their topology under consideration of electrically related other mask levels (e.g., metal + via = contact pad). We describe the implementation of a generic DRC for the detection of jogs and notches using this approach and highlight the stability and ease of maintenance of this method.
For advanced technology nodes, a large amount of effort must be spent to optimize area critical full-custom layouts with respect to their manufacturability. Due to the strong irregularity and two-dimensionality of these layouts, it appears impossible to fully capture the corresponding complex requirements with design rules in order to be able to perform a rule-based physical verification in form of a "design rule check" (DRC). Alternative approaches have to be found and one of them is presented in this paper. The complexity of the DRC can be significantly reduced for rules focused on process aspects. Those rules can be replaced by a "simulation rule check" (SRC), where at first process simulations (like e.g. lithography) are done and then a set of straightforward rules is applied to geometrical entities representing the simulation output instead of the layout geometry. Thus, this new set of rules works more directly on the core of the matter. The "litho-friendly design environment" (LFD) provided by Mentor Graphics offers the tools for this approach. The SRC includes intra-layer checks like area, width, and space checks as well as interlayer checks, such as overlap. To the physical designer, SRC violations are presented in a DRC like fashion, including error scoring and classification. This paper will demonstrate the application of LFD and highlight the usability of this infrastructure for layout optimization using an SRC for physical verification.
Lately, "Design for Manufacturability" (DFM) can be found in almost any self-respecting EDA vendor's top-five list of most critical and urgent strategic topics. While the envisioned DFM activities cover a broad spectrum of topics, the exact definition of DFM continues to evade capture . However, it appears self-evident that an important portion of DFM hinges upon the availability of models accurately describing the pattern transfer from the layout to the wafer, here called "pattern transfer models" (PTMs). In combination with a suitable design environment, PTMs will allow physical designers to optimize their layout, thus ensuring the structural integrity over the process window upon transfer to the wafer. In this paper, we argue that PTMs have an importance comparable to that of the "electrical device models" (EDMs) widely used for circuit simulation. We point out some striking analogies between PTMs and EDMs, as far as the basic concepts and use models are concerned. Furthermore, we highlight the significant differences in the EDA land-scapes for both model types, most importantly the fact that an industry standard only exists for EDMs. Based on the consequences for EDA vendors and users, as well as manufacturing cooperations that derive from this situation, we formulate the call for an industry standard for PTMs for usage in "Optical Proximity Correction" (OPC) and DFM.
Recently, "design for manufacturability" (DFM) has become a veritable buzzword in the semiconductor manufacturing community. DFM activities cover a broad spectrum ranging from the improvement of the electrical and structural robustness against process variations to the reduction of layout parts critical for statistically distributed defects or sensitive to systematic process weaknesses. In our work we focus only on those aspects of DFM concerned with the structural integrity of patterns on the wafer. We show that a purely geometrical analysis of product layouts offers a powerful tool to strengthen the link between design and manufacturing. It allows, for instance, a visualisation of the extent to which intra- and inter-layer design rules determine the geometry configurations dominating the layout and the identification of patterns occurring only rarely. Furthermore, in combination with the geometry-resolved information about the accuracy of "optical proximity correction" (OPC) models and "critical dimension" (CD) control, such an analysis provides valuable input for systematic improvements on both, the product layout and manufacturing process side. In this sense it supports the progress towards making real designs still manufacturable at the limits of process tool capabilities.
Use of simulation-based printing verification prior to mask tapeout has become standard practice for mask layers printed with low-k1 lithography processes. At 90nm and above, this methodology has proven beneficial and sufficient for guaranteeing a usable mask. However, it is anticipated that at 65nm and below, a simulation at a single point within the process window may fail to capture all important marginal areas of a mask prior to tapeout. Modern lithography simulation tools are proven capable of accurately predicting printing behavior through process window. Unfortunately, due to long run times, use of such tools is restricted to small simulation areas. Recent developments in vectorial thin-film OPC models have enabled full process window prediction on large product die. Although such models are extremely fast compared to conventional lithography simulation tools, the prospect of simulating a full chip at multiple dose and focus points is quite daunting. In an effort to reduce the expected longer run times when simulating full chips at multiple focus and dose conditions, we have developed two flows which reduce the total run time enormously. These so-called pre-targeting flows are explained, and the limitations and future prospects of the flows are described.
Traditionally, there has been a clear separation between TCAD and full chip simulation tools. While TCAD is normally used during process development, it remains outside the realm of full chip corrections due to its long runtime requirements.
One of the key components of a model-based OPC tool is fast and reliable CD prediction of all features present in the design layout, usually at the best point in the process window. Such models exist today, and are routinely used in production. However, there is also a growing need to make more informed decisions about the tradeoffs between accuracy, correction and turn around time. For this reason we need to develop techniques that enable full chip simulations across a variety of process conditions. It was previously shown that a combination of optical vector and variable threshold models can be calibrated to predict well across multiple focus conditions, however dose predictions have not yet been studied.
In principle, the possibility of having models that predict process window behavior exists today by calibrating empirical models separately at every one of the process conditions under investigation. However, this method has two clear disadvantages. On the one hand, it cannot guarantee that such models can be extrapolated to conditions other than those used for their calibration, thus not making it possible to provide models "on demand" for arbitrary focus and dose values. And on the other hand, a substantial additional effort is required for creating models at more than one process condition.
This work concentrates in listing the requirements to evaluate the robustness of any process window model as well as showing how a well-calibrated compact model can be used to predict -within metrology uncertainty- dose and defocus induced changes for a wide variety of features. While such capability has a number of applications, we will
describe a methodology for IC-product verification.
With advanced CMOS technologies, model-based optical proximity correction (OPC) has become the most important aspect of post-tape-out data preparation for critical mask levels. While fabrication processes certainly remain the foundation of a qualified
technology, the quality of OPC is increasingly moving into the focus of efforts to further improve yield. For a typical model-based OPC tool, the full OPC model consists of two distinct parts: (1) An aerial image part, based on a few, well-defined optical parameters of the lithography tool to describe the light intensity
distribution in air at the wafer level and (2) an empirical part to model all other aspects of the pattern transfer, based on different black box modeling techniques such as kernel convolution or variable threshold modeling. Most importantly, the parameters for the empirical part are usually determined by fitting the model to proximity data measured from test structures. As a consequence, the robustness of the full OPC model for productive usage correlates directly with the extent to which these test structures provide a representative sampling of the circumstances encountered in an actual product layout. In order to determine the quality of this sampling, full-chip aerial image analyses are performed for various mask levels of a product design. A comparison of the characteristics of the light intensity distributions of this design with the corresponding
information obtained from the test structures reveals configurations that are not well covered by the latter. This insight allows the definition of suitable additional test structures in order to improve the robustness of subsequent empirical OPC models.