In DRAM technology, rapidly decreasing critical dimensions cause a strong need in lithography for optimization of illumination conditions. In critical line levels, this will lead to an increasing demand for application of different, specially optimized illuminations to differently structured layout portions. Such a strategy can be achieved by double exposure techniques. A major technical challenge in this approach is the case in which electrically connected layout regions are assigned to different litho illuminations. Here, the layout separation onto different masks must preserve a sufficient process window in the electrically connected layout cut regions. A key success factor is a double exposure aware OPC strategy, able to describe and correct layouts defined by the interaction of two exposures with different illumination settings. In our contribution, we present the results of a double exposure experiment for a critical metal level. A likewise mask-manufacturing-friendly and litho-friendly method of layout separation on 'double tri-tone masks' was developed. Mask and wafer results show the principal feasibility of the chosen concept and prove the necessary OPC functionality.