This paper discusses several metasurface structures for optimizing the performance of silicon-based SPAD single-photon detectors, enabling them to overcome the material bandgap limitation of silicon and achieve a significant enhancement in absorption efficiency in the wavelength range above 1100nm. The mentioned metasurface structures consist of periodic arrays and utilize Surface Plasmon Resonance (SPR) and three-dimensional cavity effects to induce strong electric field enhancement at the metal-silicon interface through the excitation of Surface Plasmon Polaritons (SPPs). This imparts the detector with a strong light-capturing capability. The performance differences in absorption efficiency among these metasurface structures are elaborated upon, and the feasibility of their integration with SPAD single-photon detectors is discussed.
This paper proposes an approach based on numerical simulation to enhance the accuracy and generality of fringe field modeling in Quadrupole Mass Filter (QMF) systems. The proposed method involves SIMION simulation calculations to achieve the desired outcomes. A numerical model of the potential distribution is constructed using the finite numerical difference method in the region where the QMF and end plate are connected. The exponential fringe field function is selected as the basis for approximation, and the fringe field function is obtained through the least squares method. The potential gradient curves for different end plate gaps are derived, revealing the impact of gaps on the fringe field intensity, length, and penetration into the QMF. The proposed method is validated by comparing the obtained fringe field analysis model with literature data The research establishes the reliability and validity of the proposed method for effectively analyzing the fringe fields between the end plate and the QMF electrode in QMF systems.This makes it possible to study the properties of such systems by phase-space dynamics methods.
In this paper, an optimized structure of single photon avalanche diode (SPAD) with p-i-n construction is presented, and the device is compatible with standard CMOS technology. TCAD software and accurate calculation method based on physics mechanism are employed for the device structure design and DCR calculation, respectively. The characteristic parameters of the device, such as electric field and electron and hole triggering probability, are available through TCAD Atlas device simulation. The central region of P-sub doping is designed as a part of avalanche region, which achieves a lower electric field, and makes the band-to-band tunneling suppressed simultaneously. The breakdown voltage of the SPAD is 38.5 V. At excess bias voltage of 5 V, DCR is 0.88 Hz/μm2 at room temperature. The maximum electric field of the optimized structure is 3.8×105 V/cm. As for PDE, at room temperature with 5.0 V excess bias, the PDE is greater than 30% in the 400 nm-675 nm range, with a peak PDE of 40% at 550 nm. At 850 nm, there is still a photon detection efficiency of more than 10%, making the SPAD still have a certain detection capability. The superior performance of this structure makes it suitable for wide applications.
We present a novel backside-illuminated single photon avalanche diode (SPAD) which is compatible with standard CMOS technology. The structure of SPAD is based on p-i-n junction which is the first time to be used to backsideilluminated structure, thus enabling a significantly low dark count rate (DCR). In order to get better photon detection efficiency (PDE) in near-infrared , we optimized the junction width and thickness of the device. The structure of SPAD is designed by the TCAD Devedit tool, and some important characteristic parameters are extracted by the Atlas tool. We calculate DCR and PDE using the extracted parameters. At 5 V excess bias voltage, the DCR of 0.81 Hz/μm2 is achieved at room temperature. The PDE at 5 V excess bias voltage is 20%. The fill factor is up to 53%. The DCR of the structure has reached the international advanced level.
The CMOS single photon avalanche photodiode (SPAD) image sensor, as the third-generation solid-state imaging device, features single photon response capability, picosecond magnitude time resolution and micron-scale spatial resolution. The device is currently the mainstream ideal device for single-photon, picosecond time-resolved transient imaging, and is gradually applied to time-resolved spectral measurement, 3D ranging and imaging, fluorescence lifetime imaging, quantum imaging sensing and such low light or even single photon ultrafast imaging. In this paper, we introduce the research progress of the CMOS SPAD image sensor, and the challenges and solutions of the device are analyzed. In the past years, the mainstream CMOS SPAD image sensor features front-illuminated SPAD and the planar-structure pixel. However, for the planar-structure pixel, in order to make the SPAD with higher fill factor, reducing the duty cycle of the readout electronics within the pixel is the usual method, which to some extent sacrifices the function of reading electronics. In addition, the lower process node was used to improve the integration of electronics, but the high dark count rate was easily caused; The integration of micro-lens array in pixels was also used, but limits the flexibility of pixel size and increases the costs. Compared with planar-structure pixel, the pixel scheme of the three dimensional (3D) stacked structure, integrates the SPAD device and the readout electronics in the pixel correspondingly on the vertically coupled two wafers, which eliminates the problem of duty cycle of the readout electronics within the pixel and would be the development direction in the future.
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