Dr. Timothy Tsuei Profile

Dr. Timothy Tsuei

Program Manager at Synopsys Inc

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Publications (3)

Proceedings Article | 30 April 2023 Presentation

A Synopsys TCAD-based workflow to support technology evaluation at 3nm and beyond

Robert Robison, Janet Wilson, Reinaldo Vega, Terence Hook, Frank Geelhaar, Jonathan Cobb, Tim Tsuei

Proceedings Volume 12495, 1249510 (2023) https://doi.org/10.1117/12.2658572

KEYWORDS: Transistors, Device simulation, Back end of line, TCAD, Standards development, Process modeling, Performance modeling, Oscillators, New and emerging technologies, Multilayers

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Proceedings Article | 23 March 2020 Presentation + Paper

Multi-varied implementations with common underpinnings in design technology co-optimization

Kevin Lucas, Victor Moroz, John Kim, Soo-Han Choi, Tim Tsuei

Proceedings Volume 11328, 113280Y (2020) https://doi.org/10.1117/12.2553656

KEYWORDS: Device simulation, Optical lithography, Silicon, Semiconducting wafers, Process modeling, Visualization, Lithography, Design for manufacturing

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Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.

Proceedings Article | 6 December 2004 Paper

Resolution enhancement technique optimization using model-based full-chip verification methodology for subwavelength lithography

Juhwan Kim, Minghui Fan, Lantian Wang, Timothy Tsuei, Zongwu Tang

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.569294

KEYWORDS: Optical proximity correction, Resolution enhancement technologies, Data modeling, Lithography, Optical lithography, Process modeling, Photomasks, Error analysis, Critical dimension metrology, Bridges

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