Fueled by higher bandwidth wireless communication and ubiquitous AI, the demand for more affordable and power efficient transistors is accelerating at a time when Dennard scaling is undeniably crawling to a halt. Escalating wafer and design cost are commonly identified as the primary culprits bringing Moore's law to its knees. However, a third component: the cost of making the wrong technology choice early in the development cycle, is equally responsible for slowing the progress of the semiconductor industry. The enormous complexity of leading edge technology nodes has been achieved incrementally over time by limiting each technology node to mostly small evolutionary steps. Forcing too much innovation in one technology node would have catastrophically disrupted the continuous learning curve. As we approach the fundamental device-physics and material-science limits of dimensional scaling, we are forced to look at far more disruptive device and interconnect innovations to achieve meaningful power-performance-area-cost (PPAC) improvement. For example, the complexity versus benefit tradeoffs of innovative 3-dimensional device architectures with non-standard power-distribution networks are so hard to quantify that rigorous yet efficient prototyping becomes indispensable even prior to committing foundry R&D resources. In this paper we present our work on developing a purpose-built suite of tools to vastly accelerate the quantitative pre-screening and optimization of technology options to help the industry maintain its relentless pace of PPAC scaling. We share several examples that demonstrate how we tune a candidate technology definition with this tool-suite. We also describe the important common technologies in successful Design Technology Co-Optimization (DTCO) flows including physical material and process modeling; electrical and circuit simulation; detailed design analysis and modification to reduce weak points; handling enormous datasets; silicon learning feedback loop and intuitive visualization.
Resolution enhancement techniques and OPC(Optical Proximity Correction) have been developed with empirical data points from general test patterns and some actual patterns extracted from full-chip design. Lithography simulation tools have been used for intensive process simulation to optimize RET solutions using sample patterns to cover whole full-chip patterns. However, as design complexity increases and mask manufacturing rules restrict process proximity correction coverage, post-RET/OPC data can generate fatal patterning failures at locations where the process window is marginal. Therefore, it is necessary to identify those patterns from full-chip layout to choose proper RET/OPC solutions. Previously, it was proven that model based full-chip verification tool is useful to capture potential fatal patterning failures before mask tape-out sign-off for sub-wavelength lithography processes.  In this paper, we extended the full-chip verification methodology to quantitative RET/OPC development using database error analysis. First, using GDS data containing design intent only and a single 90nm lithography process calibrated model, we performed full-chip verification for linearly scaled designs through 130nm, 90nm and 65nm node to take OPC directions. Second, a standard OPC recipe was applied for each design node followed by verification. And then, potential pattern failures at 65nm node were analyzed through lithography process window. Finally, RET/OPC solution was discussed for 65nm design.