This paper presents a new method for run-time management of shared processing resources in multiprocessor systems on chip. A centralized resource manager unit performs dynamic allocation of shared processing resources according to the system state and given constraints. It implements a hardware mutual exclusion so that no inter-processor synchronization is required for accessing the resources. Moreover, it supports dynamic power management. In addition, a hardware implementation of the resource manager is proposed. In a case study, a resource manager is evaluated in a data-parallel MPEG-4 video encoder on multiprocessor system on chip on FPGA. The RM eases the design of six different architectures featuring two to twelve shared hardware accelerators. Only a few accelerators are required for the best performance as the accesses are efficiently scheduled.
The paper presents a novel scheme of dynamic power management for UML modeled applications that are executed
on a multiprocessor System-on-Chip (SoC) in a distributed manner. The UML models for both application
and architecture are designed according to a well-defined UML profile for embedded system design, called TUT-Profile.
Application processes are considered as elementary units of distributed execution, and their mapping on
a multiprocessor SoC can be dynamically changed at run-time. Our approach on the dynamic power management
balances utilized processor resources against current workload at runtime by (1) observing the processor
and workload statistics, (2) re-evaluating the amount of required resources (i.e. the number of active processors),
and (3) re-mapping the application processes to the minimum set of active processors. The inactive processors
are set to a power-save state by using clock-gating. The approach integrates the well-known power management
techniques tightly with the UML based design of embedded systems in a novel way. We evaluated the dynamic
power management with a WLAN terminal implemented on a multiprocessor SoC on Altera Stratix II FPGA
containing up to five Nios II processors and dedicated hardware accelerators. Measurements proved up to 21%
savings in the power consumption of the whole FPGA board.
Feasibility of DSP/BIOS real-time operating system for a multi-channel MPEG-4 encoder is studied. Performances of two MPEG-4 encoder implementations with and without the operating system are compared in terms of encoding frame rate and memory requirements. The effects of task switching frequency and number of parallel video channels to the encoding frame rate are measured. The research is carried out on a 200 MHz TMS320C6201 fixed point DSP using QCIF (176x144 pixels) video format. Compared to a traditional DSP implementation without an operating system, inclusion of DSP/BIOS reduces total system throughput only by 1 QCIF frames/s. The operating system has 6 KB data memory overhead and program memory requirement of 15.7 KB. Hence, the overhead is considered low enough for resource critical mobile video applications.