In this paper, the impact of resist on the lithographic process window is investigated. To estimate the resolution
limit of EUVL due to the limitation from resist performance, a simplified resist model, called diffused aerial image
model (DAIM), is employed. In the DAIM, the resist is characterized by the acid diffusion length, or more generally,
resist blur. Lithographic process windows with resists of various blurs are then calculated for different technology nodes.
It is concluded that the resist blur needs to be smaller than 8 nm to achieve a reasonable window for the technology node
with the minimum pitch of 32 nm. The performance of current resists can barely fulfill this requirement. Investigation of
a more refined resist model is also initiated.
In this paper, definition of line/space patterns at 44-, 32-, and 22-nm pitches using extreme-ultraviolet lithography
(EUVL) is investigated by aerial image simulation. The results indicate that extending EUVL to the 22-nm pitch requires
reducing the mask shadowing effect, which implies reducing the mask absorber thickness as well as maintaining the
6-degree angle of incidence on the mask, if the reduction ratio of the imaging system is to be kept at 4. Reduction of the
mask absorber thickness can be realized by implementing attenuated phase-shifting masks. Otherwise, all critical
patterns must be laid out in single orientation.
A programmed-defect mask consisting of both bump- and pit-type defects on the LTEM mask substrate has been
successfully fabricated. It is seen that pit-type defects are less printable because they are more smoothed out by the
employed MLM deposition process. Specifically, all bump-type defects print even at the smallest height split of 1.7 nm
whereas pit-type defects print only at the largest depth split of 5.7 nm. At this depth, the largest nonprintable 1D and 2D
defect widths are about 23 nm and 64 nm, respectively.
Contact Hole (CH) resolution is limited by the low aerial image contrast using dark field masks. Moreover the 2-
Dimensional character of CH is a limiting factor in the use of extreme Resolution Enhancement Techniques for reaching
the smallest pitch. These limitations can be overcome if one deconvolves the 2D CH into two exposures of 1D structures
(i.e. lines). These 1D structures can indeed be printed at the ultimate resolution limit of the scanner using dipole
Recently, several materials have become available to pattern CH from such a double exposure of line patterns. It is
shown in this paper how this concept of deconvolution can be used in different techniques:
Two 1D aerial images can be recomposed in order to obtain 2D images which will subsequently be reversed into
CH. We can distinguish, on the one hand, a reversal based on the positive development of line crossings into resist pillar
patterns, on which are deposited or coated a gap-fill material layer. The pillars are then removed, leaving a masking
material layer with holes. On the other hand, negative tone development can be used to reverse directly the recomposed
2D aerial image: while the classical positive development creates pillars, the negative tone development inverses
immediately this image to create contact holes in the resist layer.
In this paper, we demonstrate the potential of the double exposure method. We characterise three reversal
techniques using a NA=1.35 immersion scanner for patterning 40nm or lower CH at pitch 80nm. We also show etch
performance of these processes and address the complexity of each solution.
As the patterning of IC manufacturing shrinks to the 32-nm node and beyond, high-NA and immersion lithography are
required for pushing resolution to its physical limit. To achieve good OPC performance, various physical effects such as
polarization, mask topography, and mask pellicle have to be considered to improve the model accuracy.
The attenuation and the phase variation of TE and TM wave components induced by the pellicle would impact optical
qualities in terms of resolution, distortion, defocus shift, and high-order aberrations. In this paper, the OPC model
considering pellicle effects is investigated with Jones pupil. The CD variation induced by the pellicle effect can be
predicted accurately. Therefore, the improvement on model accuracy for 32-nm node is demonstrated.
In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.
As K1 approaching close to 0.3, it will require combinations of all the possible resolution enhancement techniques to achieve acceptable process window. In this study, we have explored the printability of 0.11μm half pitch with 0.7NA KrF lithography. We have designed several phase shifting masks to test the feasibility of printing 0.11μm half pitch line/space and dense post structures. Line and space patterns can be printed with attenuating phase shifting mask with sufficient process window. Post printing is more challenging due to its 2D optical interference effect. Chrome-less phase shifting mask is used for post printing due to its higher contrast. We have optimized mask bias and resist process in order to gain an acceptable process window. Negative KrF resist was also explored for its post printing capability. Our current study shows that the chrome-less phase shifting mask technology is capable of pushing K1 factor close to 0.3 for post printing.