The BCT solution is an automatic correction for systematic offset built into the PCS product based on calibration from 2-5 wafers. This paper explores the validity of a predictive model for process control for use by manufacturers of semiconductor devices with a multitude of products or part numbers. The proposed model defines the parameters of interests as a function of the film stack, tool attributes, and mask characteristics. The paper proposes a process for model development that dramatically reduces the cost of materials, tool time, and engineering effort.
193nm lithography has become increasingly important as the critical dimensions of semiconductor devices continue to scale down towards sub 0.10um dimension. From dry etching perspective, however, 193nm resist brings new challenges due to its poorer plasma etch resistance, line edge roughness and lower thickness compared to 248nm DUV resist. Consequently, issues such as line edge roughness and poor profile control were observed after dry etch processing. This paper presents a successful development of advanced 0.1 μm metal gate application using 193nm lithography on Applied Materials’ decoupled plasma etcher DPSII system. The integrated process involves a hard mask open with ex-situ resist strip followed by metal/poly dual gate etching. Process chemistry and process parameters for nitride mask step were thoroughly explored and investigated. With CF4/CHF3 based chemistry, the process achieved a greater then 2:1 selectivity with straight nitride profile and smooth sidewall. Less than 7nm 3-sigma of CD bias uniformity was obtained across the wafer with edge exclusion up to 4mm on a 200mm substrate. Process parameters such as pressure, gas ratio and the total Fluorine-contained flow were proven to be the most influential on resist selectivity, profile and CD control. A careful balance needs to be maintained in order to deliver an overall process. The following W/WN/poly gate etch features a three-step approach that has produced straight profiles, excellent CD control and excellent gate oxide integrity. Post-etch measurement of line edge roughness shows an average of 5nm LER. It was observed LER is a strong function of etch chemistry, reaction regime, etc. A detailed study showing methods to reduce LER is presented in this paper.
Studies on photomask Cr and MoSi etch processes were carried out and etch kinetics and modeling were performed. The photomasks were etched using an AMAT Centura II DPS and compared with a Unaxis VLE 770 ICP etcher. Mask metrology to support theoretical suppositions was performed on several tools: a KLA-Tencor P-12 profiler was used for depth measurement, while the KLA-Tencor 8250XP-R SEM was used for CD metrology and process characterization. The Toshiba EBM3500 50KeV writing system on positive chemically amplified resist was used for pattern creation. Cr and MoSi loading - etch rate equations were theoretically proposed and experimentally tested. It was found that the calculated Cr and MoSi etch rates agreed well with the experimental results. The equations can be used for etch time calculations and endpoint determinations of extremely low Cr load photomasks. Cr and MoSi local etch rates versus local loading on one photomask were studied and kinetic equations were proposed, showing good agreement with experimental results. Cr and MoSi etch CD movements versus local load on one photomask were also investigated. It was found that load effects on Cr and MoSi etch CD movements could be controlled in opposite directions and then a compensation consideration was proposed in MoSi optimization instead of using a point-to-point 3σ as the optimization parameter. By using this compensation method, the final MoSi CD unformity of 100-110 nm technology node photomasks is in the range of 8.5 to 10.1 nm. This final CD uniformity is similar to those etched using VLR 770 ICP etcher.