The bi-material concept for room-temperature infrared imaging has the potential of reaching an NE(Delta) T approaching the theoretical limit because of its high responsivity and low noise. The approach, which is 100% compatible with silicon IC foundry processing, utilizes a novel combination of surface micromachining and conventional integrated circuits to produce a bimaterial thermally sensitive element that controls the position of a capacitive plate coupled to the input of a low noise MOS amplifier. This approach can achieve the high sensitivity, the low weight, and the low cost necessary for equipment such as helmet-mounted IR viewers and IR rifle sights. The pixel design has the following benefits: (1) an order of magnitude improvement in NE(Delta) T due to extremely high sensitivity and low noise; (2) low cost due to 100% silicon IC compatibility; (3) high image quality and increased yield due to ability to do offset and sensitivity corrections on the imager, pixel-by-pixel; (4) no cryogenic cooler and no high vacuum processing; (5) commercial applications such as law enforcement, home security, and transportation safety.
The design and performance of a compact infrared camera system is presented. The 3 - 5 micron MWIR imaging system consists of a Stirling-cooled 640 X 480 staring PtSi infrared focal plane array (IRFPA) with a compact, high-performance 12-bit digital image processor. The low-noise CMOS IRFPA is X-Y addressable, utilizes on-chip-scanning registers and has electronic exposure control. The digital image processor uses 16-frame averaged, 2-point non-uniformity compensation and defective pixel substitution circuitry. There are separate 12- bit digital and analog I/O ports for display control and video output. The versatile camera system can be configured in NTSC, CCIR, and progressive scan readout formats and the exposure control settings are digitally programmable.
A new gimbal-based, FLIR camera for several types of airborne platforms has been developed. The FLIR is based on a PtSi on silicon technology: developed for high volume and minimum cost. The gimbal scans an area of 360 degrees in azimuth and an elevation range of plus 15 degrees to minus 105 degrees. It is stabilized to 25 (mu) Rad-rms. A combination of uniformity correction, defect substitution, and compact optics results in a long range, low cost FLIR for all low-speed airborne platforms.
Field deployable, high frame rate visible CCD camera systems have been developed to support the Test and Evaluation activities at the White Sands Missile Range. These visible cameras are designed around a Sarnoff 1024 X 1024 pixel, backside illuminated CCD with a 32-port, split-frame transfer architecture. The cameras exploit this architecture to provide selectable modes from a 30 Hz frame rate at 1024 X 1024 pixels to a 300 Hz frame rate with 1024 X 512 pixels (2:1 vertical binning). The cameras are configured with a 500 mm, f/4 lens, and a Ferro-electric liquid crystal electro-optic shutter, to provide variable integration times from 0.5 to 32 msec. Video outputs provided are RS170 analog video in a reduced 512 X 480 pixel format, and 12-bit full resolution digital video data stream provided through a high speed serial/parallel digital coaxial interface. At a frame rate of 300 frames per second, these cameras deliver video data at an average rate of 1.9 Gbits/sec, and a burst rate of 2.8 Gbits/sec, with the capability of reaching an average 12 bit digital data rate of 3.8 Gbits/sec when higher frame rate imagers become available.
Field deployable, high frame rate camera systems have been developed to support the test and evaluation activities at the White Sands Missile Range. The infrared cameras employ a 640 by 480 format PtSi focal plane array (FPA). The visible cameras employ a 1024 by 1024 format backside illuminated CCD. The monolithic, MOS architecture of the PtSi FPA supports commandable frame rate, frame size, and integration time. The infrared cameras provide 3 - 5 micron thermal imaging in selectable modes from 30 Hz frame rate, 640 by 480 frame size, 33 ms integration time to 300 Hz frame rate, 133 by 142 frame size, 1 ms integration time. The infrared cameras employ a 500 mm, f/1.7 lens. Video outputs are 12-bit digital video and RS170 analog video with histogram-based contrast enhancement. The 1024 by 1024 format CCD has a 32-port, split-frame transfer architecture. The visible cameras exploit this architecture to provide selectable modes from 30 Hz frame rate, 1024 by 1024 frame size, 32 ms integration time to 300 Hz frame rate, 1024 by 1024 frame size (with 2:1 vertical binning), 0.5 ms integration time. The visible cameras employ a 500 mm, f/4 lens, with integration time controlled by an electro-optical shutter. Video outputs are RS170 analog video (512 by 480 pixels), and 12-bit digital video.
The design and performance of a third generation 640(H) X 480(V) PtSi focal plane array is presented. The 3 to 5 micron MWIR focal plane array supports interlaced, progressive scan, and subframe readout under control of on-chip digital decoders. The new design utilizes 1.25 micrometers design rules to achieve a 50% fill-factor, a noise equivalent delta temperature of <0.07 C (f/1.5, 30 Hz, 300 K), and a saturation level >1.5 X 106e. The power dissipation is less than 110 mW.
The performance of a 640 x 480 PtSi, 3,5 microns (MWIR), Stirling cooled camera system with a minimum resolvable temperature of 0.03 is considered. A preliminary specification of a full-TV resolution PtSi radiometer was developed using the measured performance characteristics of the Stirling cooled camera. The radiometer is capable of imaging rapid thermal transients from 25 to 250 C with better than 1 percent temperature resolution. This performance is achieved using the electronic exposure control capability of the MOS focal plane array (FPA). A liquid nitrogen cooled camera with an eight-position filter wheel has been developed using the 640 x 480 PtSi FPA. Low thermal mass packaging for the FPA was developed for Joule-Thomson applications.
A Stirling cooled 3 - 5 micron camera system has been developed. The camera employs a monolithic 640 X 480 PtSi-MOS focal plane array. The camera system achieves an NEDT equals 0.10 K at 30 Hz frame rate with f/1.5 optics (300 K background). At a spatial frequency of 0.02 cycles/mRAD the vertical and horizontal Minimum Resolvable Temperature are in the range of MRT equals 0.03 K (f/1.5 optics, 300 K background). The MOS focal plane array achieves a resolution of 480 TV lines per picture height independent of background level and position within the frame.
The design and performance of a 640 (H) X 480 (V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. The imager achieves an NEDT equals 0.10 K at 30 Hz frame rates with f/1.5 optics (300 K background). The MOS design provides a measured saturation level of 1.5 X 106 electrons (5 V bias) and a noise floor of 300 rms electrons per pixel. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non-interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS 170 operation) resulting in `electronic shutter' variable exposure control. The pixel size of 24 micrometers X 24 micrometers results in a fill factor of 38% for 1.5 micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.
The design of a 1st and 2nd generation 640(H) X 480(V) element PtSi Schottky-barrier infrared image sensor employing a low-noise MOS X-Y addressable readout multiplexer and on-chip low-noise output amplifier is described. Measured performance characteristics for Gen 1 devices are presented along with calculated performance for the Gen 2 design. A multiplexed horizontal/vertical input address port and on-chip decoding is used to load scan data into CMOS horizontal and vertical scanning registers. This allows random access to any sub-frame in the 640 X 480 element focal plane array. By changing the digital pattern applied to the vertical scan register, the FPA can be operated in either an interlaced or non- interlaced format, and the integration time may be varied over a wide range (60 microsecond(s) to > 30 ms, for RS170 operation) resulting in a form of 'electronic shutter,' or variable exposure control. The pixel size of 24-micrometers X 24-micrometers results in a fill factor of 38% for 1.5-micrometers process design rules. The overall die size for the IR imager is 13.7 mm X 17.2 mm. All digital inputs to the chip are TTL compatible and include ESD protection.
A new concept, the Direct Schottky Injection (DSI), is described for a three-dimensional construction of infrared imagers with a continuous Schottky-barrier-detector surface on one side of a thinned (10 to 25 microns) silicon substrate and p-type buried-channel CCD readout structure on the other side. The DSI structure provides a 100-percent fill factor, a large charge-handling capacity, and a high-density pixel design. The construction and operation are described for DSI imagers with frame-transfer CCD (FT-CCD) and interline-transfer CCD(IT-CCD) readout. The operation of the IT-CCD DSI imager was demonstrated with a 128 x 128 focal plane array (FPA) with 50 x 50-micron pixels.
The design of a 640 by 480 element PtSi IR sensor is presented which includes a low-noise MOS X-Y addressable readout multiplexer and an on-chip correlated double-sampling amplifier. The sensor is designed to load scan data into CMOS horizontal and vertical scanning registers by means of a multiplexed horizontal/vertical input address port and onchip decoding, allowing any element in the focal plane array to be randomly accessed. The FPA is shown to be operable in both the interlaced and noninterlaced formats, with variable exposure control. Enhanced noise performance is shown due to the use of buried channel source follower buffers in the horizontal signal lines. It was shown that 24 micron square pixels with a 1.5 micron double level metal CMOS process provide a fill factor of 38 percent. TTL compatibility and ESD protection diodes are key features of the digital inputs to the sensor's chip.